rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Signals
data_valid_i	std_logic
icode_i	std_logic_vector ( 1 downto 0 )
byte_i	std_logic_vector ( 7 downto 0 )
ready_i	std_logic
new_data_i	std_logic
read_i	std_logic
write_i	std_logic
start_i	std_logic
stop_i	std_logic
error_i	std_logic
word_i	std_logic_vector ( 9 downto 0 )
addib_i	std_logic_vector ( 2 downto 0 )
data_result_i	std_logic_vector ( 15 downto 0 )
dataresult_fsc_i	std_logic_vector ( 20 downto 0 )
ih_busy_i	std_logic
rnw_i	std_logic
exec_id_i	std_logic
rnw_id_i	std_logic
branch_id_i	std_logic
fec_add_id_i	std_logic_vector ( 3 downto 0 )
bcreg_add_id_i	std_logic_vector ( 7 downto 0 )
bcdata_id_i	std_logic_vector ( 15 downto 0 )
exec_i	std_logic
rwn_i	std_logic
branch_i	std_logic
bcast_i	std_logic
fec_add_i	std_logic_vector ( 3 downto 0 )
bcreg_add_i	std_logic_vector ( 7 downto 0 )
bcdata_i	std_logic_vector ( 15 downto 0 )
csr1_i	std_logic_vector ( 13 downto 0 )
scl_i	std_logic
sda_in_i	std_logic
master_end_i	std_logic
data_fbc_i	std_logic_vector ( 7 downto 0 )
cnt_rx_i	std_logic
seq_active_i	std_logic
Component Instantiations
sequencer_rcu_1	msm_sequencer_rcu <Entity msm_sequencer_rcu>
instr_builder_1	msm_instr_builder <Entity msm_instr_builder>
master_1	msm_master <Entity msm_master>
interrupt_driver_1	msm_interrupt_driver <Entity msm_interrupt_driver>
mux_signals_1	msm_mux_signals <Entity msm_mux_signals>
sc_signals_1	msm_sc_signals <Entity msm_sc_signals>

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Member Data Documentation

addib_i std_logic_vector ( 2 downto 0 ) [Signal]

bcast_i std_logic [Signal]

bcdata_i std_logic_vector ( 15 downto 0 ) [Signal]

bcdata_id_i std_logic_vector ( 15 downto 0 ) [Signal]

bcreg_add_i std_logic_vector ( 7 downto 0 ) [Signal]

bcreg_add_id_i std_logic_vector ( 7 downto 0 ) [Signal]

branch_i std_logic [Signal]

branch_id_i std_logic [Signal]

byte_i std_logic_vector ( 7 downto 0 ) [Signal]

cnt_rx_i std_logic [Signal]

csr1_i std_logic_vector ( 13 downto 0 ) [Signal]

data_fbc_i std_logic_vector ( 7 downto 0 ) [Signal]

data_result_i std_logic_vector ( 15 downto 0 ) [Signal]

data_valid_i std_logic [Signal]

dataresult_fsc_i std_logic_vector ( 20 downto 0 ) [Signal]

error_i std_logic [Signal]

exec_i std_logic [Signal]

exec_id_i std_logic [Signal]

fec_add_i std_logic_vector ( 3 downto 0 ) [Signal]

fec_add_id_i std_logic_vector ( 3 downto 0 ) [Signal]

icode_i std_logic_vector ( 1 downto 0 ) [Signal]

ih_busy_i std_logic [Signal]

instr_builder_1 msm_instr_builder [Component Instantiation]

interrupt_driver_1 msm_interrupt_driver [Component Instantiation]

master_1 msm_master [Component Instantiation]

master_end_i std_logic [Signal]

mux_signals_1 msm_mux_signals [Component Instantiation]

new_data_i std_logic [Signal]

read_i std_logic [Signal]

ready_i std_logic [Signal]

rnw_i std_logic [Signal]

rnw_id_i std_logic [Signal]

rwn_i std_logic [Signal]

sc_signals_1 msm_sc_signals [Component Instantiation]

scl_i std_logic [Signal]

sda_in_i std_logic [Signal]

seq_active_i std_logic [Signal]

sequencer_rcu_1 msm_sequencer_rcu [Component Instantiation]

start_i std_logic [Signal]

stop_i std_logic [Signal]

word_i std_logic_vector ( 9 downto 0 ) [Signal]

write_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• msmodule/msm_lsc_core/msm_lsc_core.vhd