msm_interrupt_driver Entity Reference

Inheritance diagram for msm_interrupt_driver:

Collaboration diagram for msm_interrupt_driver:

Architectures
rtl	Architecture
Libraries
ieee
msmodule_lib
Packages
std_logic_1164
msm_cards_status_pack	Package <msm_cards_status_pack>
msm_interrupt_handler_pack	Package <msm_interrupt_handler_pack>
Ports
clk	in std_logic
rstb	in std_logic
seq_active	in std_logic
fec_al	in std_logic_vector ( 31 downto 0 )
rdol	in std_logic_vector ( 31 downto 0 )
stop	in std_logic
interruptA	in std_logic
interruptB	in std_logic
csr1	in std_logic_vector ( 13 downto 0 )
master_end	in std_logic
error	in std_logic
fec_al_fsc	out std_logic_vector ( 31 downto 0 )
we_fec_al_fsc	out std_logic
rdol_fsc	out std_logic_vector ( 31 downto 0 )
we_rdol_fsc	out std_logic
ih_busy	out std_logic
exec	out std_logic
branch	out std_logic
rnw	out std_logic
fec_add	out std_logic_vector ( 3 downto 0 )
bcreg_add	out std_logic_vector ( 7 downto 0 )
data	out std_logic_vector ( 15 downto 0 )
add_sr	out std_logic_vector ( 4 downto 0 )
sr	out std_logic_vector ( 15 downto 0 )
we_sr	out std_logic
warning_to_dcs	out std_logic
inta_not_en	out std_logic
intb_not_en	out std_logic

Member Data Documentation

add_sr out std_logic_vector ( 4 downto 0 ) [Port]

bcreg_add out std_logic_vector ( 7 downto 0 ) [Port]

branch out std_logic [Port]

clk in std_logic [Port]

csr1 in std_logic_vector ( 13 downto 0 ) [Port]

data out std_logic_vector ( 15 downto 0 ) [Port]

error in std_logic [Port]

exec out std_logic [Port]

fec_add out std_logic_vector ( 3 downto 0 ) [Port]

fec_al in std_logic_vector ( 31 downto 0 ) [Port]

fec_al_fsc out std_logic_vector ( 31 downto 0 ) [Port]

ieee library [Library]

ih_busy out std_logic [Port]

inta_not_en out std_logic [Port]

intb_not_en out std_logic [Port]

interruptA in std_logic [Port]

interruptB in std_logic [Port]

master_end in std_logic [Port]

msm_cards_status_pack package [Package]

msmodule_lib library [Library]

rdol in std_logic_vector ( 31 downto 0 ) [Port]

rdol_fsc out std_logic_vector ( 31 downto 0 ) [Port]

rnw out std_logic [Port]

rstb in std_logic [Port]

seq_active in std_logic [Port]

sr out std_logic_vector ( 15 downto 0 ) [Port]

std_logic_1164 package [Package]

stop in std_logic [Port]

warning_to_dcs out std_logic [Port]

we_fec_al_fsc out std_logic [Port]

we_rdol_fsc out std_logic [Port]

we_sr out std_logic [Port]

The documentation for this class was generated from the following file: