rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Signals | |
| interrupt_i | std_logic |
| add_ready_i | std_logic |
| add_card_i | std_logic_vector ( 4 downto 0 ) |
| check_int_wait_i | std_logic |
| last_card_i | std_logic |
| read_al_i | std_logic |
Component Instantiations | |
| cards_status_1 | msm_cards_status <Entity msm_cards_status> |
| interrupt_handler_1 | msm_interrupt_handler <Entity msm_interrupt_handler> |
Member Data Documentation
add_card_i std_logic_vector ( 4 downto 0 ) [Signal] |
add_ready_i std_logic [Signal] |
cards_status_1 msm_cards_status [Component Instantiation] |
check_int_wait_i std_logic [Signal] |
interrupt_handler_1 msm_interrupt_handler [Component Instantiation] |
interrupt_i std_logic [Signal] |
last_card_i std_logic [Signal] |
read_al_i std_logic [Signal] |
The documentation for this class was generated from the following file:
- msmodule/msm_lsc_core/msm_interrupt_driver/msm_interrupt_driver.vhd
