msm_interrupt_handler Entity Reference
Inheritance diagram for msm_interrupt_handler:
Collaboration diagram for msm_interrupt_handler:
Architectures | |
| rtl | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
Ports | |
| clk | in std_logic |
| rstb | in std_logic |
| interrupt | in std_logic |
| csr1 | in std_logic_vector ( 13 downto 0 ) |
| add_ready | in std_logic |
| add_card | in std_logic_vector ( 4 downto 0 ) |
| stop | in std_logic |
| fec_al | in std_logic_vector ( 31 downto 0 ) |
| rdol | in std_logic_vector ( 31 downto 0 ) |
| seq_active | in std_logic |
| master_end | in std_logic |
| error | in std_logic |
| last_card | in std_logic |
| read_al | out std_logic |
| fec_al_fsc | out std_logic_vector ( 31 downto 0 ) |
| we_fec_al_fsc | out std_logic |
| rdol_fsc | out std_logic_vector ( 31 downto 0 ) |
| we_rdol_fsc | out std_logic |
| warning_to_dcs | out std_logic |
| ih_busy | out std_logic |
| add_sm | out std_logic_vector ( 4 downto 0 ) |
| sm | out std_logic_vector ( 15 downto 0 ) |
| we_sm | out std_logic |
| exec | out std_logic |
| branch | out std_logic |
| fec_add | out std_logic_vector ( 3 downto 0 ) |
| rnw | out std_logic |
| bcreg_add | out std_logic_vector ( 7 downto 0 ) |
| bcdata | out std_logic_vector ( 15 downto 0 ) |
| check_int_wait | out std_logic |
Member Data Documentation
add_card in std_logic_vector ( 4 downto 0 ) [Port] |
add_ready in std_logic [Port] |
add_sm out std_logic_vector ( 4 downto 0 ) [Port] |
bcdata out std_logic_vector ( 15 downto 0 ) [Port] |
bcreg_add out std_logic_vector ( 7 downto 0 ) [Port] |
branch out std_logic [Port] |
check_int_wait out std_logic [Port] |
clk in std_logic [Port] |
csr1 in std_logic_vector ( 13 downto 0 ) [Port] |
error in std_logic [Port] |
exec out std_logic [Port] |
fec_add out std_logic_vector ( 3 downto 0 ) [Port] |
fec_al in std_logic_vector ( 31 downto 0 ) [Port] |
fec_al_fsc out std_logic_vector ( 31 downto 0 ) [Port] |
ieee library [Library] |
ih_busy out std_logic [Port] |
interrupt in std_logic [Port] |
last_card in std_logic [Port] |
master_end in std_logic [Port] |
numeric_std package [Package] |
rdol in std_logic_vector ( 31 downto 0 ) [Port] |
rdol_fsc out std_logic_vector ( 31 downto 0 ) [Port] |
read_al out std_logic [Port] |
rnw out std_logic [Port] |
rstb in std_logic [Port] |
seq_active in std_logic [Port] |
sm out std_logic_vector ( 15 downto 0 ) [Port] |
std_logic_1164 package [Package] |
stop in std_logic [Port] |
warning_to_dcs out std_logic [Port] |
we_fec_al_fsc out std_logic [Port] |
we_rdol_fsc out std_logic [Port] |
we_sm out std_logic [Port] |
The documentation for this class was generated from the following file:
- msmodule/msm_lsc_core/msm_interrupt_driver/msm_interrupt_handler/msm_interrupt_handler.vhd
