rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
next_state	( clk , rstb )
fsm	( st_i , interrupt , seq_active , stop , csr1 , hard_error_i , master_end , error , last_card , cnt_wait_i )
output_addresses	( clk , rstb )
word_counter	( clk , rstb )
validated_fecs	( clk , rstb )
address_status	( clk , rstb )
wait_counter	( clk , rstb )
Types
st_t	( idle , check_sequencer , rd_reg , rd_error , int_handling , mask_error , check_stop , check_int , wait_1cycle , wait_2cycle , wait_cnt )
Signals
branch_i	std_logic
fec_add_i	std_logic_vector ( 3 downto 0 )
st_i	st_t := idle
nx_st_i	st_t := idle
hard_error_i	std_logic
soft_error_i	std_logic
csr1_ready_i	std_logic
merror_i	std_logic
wr_nwords_i	std_logic
cnt_wait_clr_i	std_logic
cnt_wait_en_i	std_logic
cnt_wait_i	unsigned ( 4 downto 0 )
cnt_word_clr_i	std_logic
cnt_word_en_i	std_logic
cnt_word_i	unsigned ( 4 downto 0 )

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Member Function Documentation

[Process]

address_status		( clk ,
		rstb )

[Process]

fsm		( st_i ,
		interrupt ,
		seq_active ,
		stop ,
		csr1 ,
		hard_error_i ,
		master_end ,
		error ,
		last_card ,
		cnt_wait_i )

[Process]

next_state		( clk ,
		rstb )

[Process]

output_addresses		( clk ,
		rstb )

[Process]

validated_fecs		( clk ,
		rstb )

[Process]

wait_counter		( clk ,
		rstb )

[Process]

word_counter		( clk ,
		rstb )

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Member Data Documentation

branch_i std_logic [Signal]

cnt_wait_clr_i std_logic [Signal]

cnt_wait_en_i std_logic [Signal]

cnt_wait_i unsigned ( 4 downto 0 ) [Signal]

cnt_word_clr_i std_logic [Signal]

cnt_word_en_i std_logic [Signal]

cnt_word_i unsigned ( 4 downto 0 ) [Signal]

csr1_ready_i std_logic [Signal]

fec_add_i std_logic_vector ( 3 downto 0 ) [Signal]

hard_error_i std_logic [Signal]

merror_i std_logic [Signal]

nx_st_i st_t := idle [Signal]

soft_error_i std_logic [Signal]

st_i st_t := idle [Signal]

st_t ( idle , check_sequencer , rd_reg , rd_error , int_handling , mask_error , check_stop , check_int , wait_1cycle , wait_2cycle , wait_cnt ) [Type]

wr_nwords_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• msmodule/msm_lsc_core/msm_interrupt_driver/msm_interrupt_handler/msm_interrupt_handler.vhd