Architectures | |
rtl | Architecture |
Libraries | |
ieee | |
Packages | |
std_logic_1164 | |
Ports | |
clk | in std_logic |
rstb | in std_logic |
add | in std_logic_vector ( 2 downto 0 ) |
rnw | in std_logic |
bcast | in std_logic |
fec_add | in std_logic_vector ( 3 downto 0 ) |
reg_add | in std_logic_vector ( 7 downto 0 ) |
data | in std_logic_vector ( 15 downto 0 ) |
word | out std_logic_vector ( 9 downto 0 ) |
add in std_logic_vector ( 2 downto 0 ) [Port] |
bcast in std_logic [Port] |
clk in std_logic [Port] |
data in std_logic_vector ( 15 downto 0 ) [Port] |
fec_add in std_logic_vector ( 3 downto 0 ) [Port] |
ieee library [Library] |
reg_add in std_logic_vector ( 7 downto 0 ) [Port] |
rnw in std_logic [Port] |
rstb in std_logic [Port] |
std_logic_1164 package [Package] |
word out std_logic_vector ( 9 downto 0 ) [Port] |