rtl Architecture Reference

Inheritance diagram for rtl:

[legend]

Collaboration diagram for rtl:

[legend]

List of all members.

Processes
output	( clk , rstb )
Constants
start	std_logic_vector ( 1 downto 0 ) := " 10 "
write	std_logic_vector ( 1 downto 0 ) := " 11 "
read	std_logic_vector ( 1 downto 0 ) := " 01 "
stop	std_logic_vector ( 1 downto 0 ) := " 00 "

---

Member Function Documentation

[Process]

output		( clk ,
		rstb )

---

Member Data Documentation

read std_logic_vector ( 1 downto 0 ) := " 01 " [Constant]

start std_logic_vector ( 1 downto 0 ) := " 10 " [Constant]

stop std_logic_vector ( 1 downto 0 ) := " 00 " [Constant]

write std_logic_vector ( 1 downto 0 ) := " 11 " [Constant]

---

The documentation for this class was generated from the following file:

• msmodule/msm_lsc_core/msm_instr_builder/msm_instr_builder.vhd