msm_mux_signals Entity Reference

Inheritance diagram for msm_mux_signals:

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Collaboration diagram for msm_mux_signals:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
Ports
ih_busy	in std_logic
exec_dcs	in std_logic
rnw_dcs	in std_logic
branch_dcs	in std_logic
bcast_dcs	in std_logic
fec_add_dcs	in std_logic_vector ( 3 downto 0 )
bcreg_add_dcs	in std_logic_vector ( 7 downto 0 )
bcdata_dcs	in std_logic_vector ( 15 downto 0 )
exec_id	in std_logic
rnw_id	in std_logic
branch_id	in std_logic
fec_add_id	in std_logic_vector ( 3 downto 0 )
bcreg_add_id	in std_logic_vector ( 7 downto 0 )
bcdata_id	in std_logic_vector ( 15 downto 0 )
exec	out std_logic
rnw	out std_logic
branch	out std_logic
bcast	out std_logic
fec_add	out std_logic_vector ( 3 downto 0 )
bcreg_add	out std_logic_vector ( 7 downto 0 )
bcdata	out std_logic_vector ( 15 downto 0 )

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Member Data Documentation

bcast out std_logic [Port]

bcast_dcs in std_logic [Port]

bcdata out std_logic_vector ( 15 downto 0 ) [Port]

bcdata_dcs in std_logic_vector ( 15 downto 0 ) [Port]

bcdata_id in std_logic_vector ( 15 downto 0 ) [Port]

bcreg_add out std_logic_vector ( 7 downto 0 ) [Port]

bcreg_add_dcs in std_logic_vector ( 7 downto 0 ) [Port]

bcreg_add_id in std_logic_vector ( 7 downto 0 ) [Port]

branch out std_logic [Port]

branch_dcs in std_logic [Port]

branch_id in std_logic [Port]

exec out std_logic [Port]

exec_dcs in std_logic [Port]

exec_id in std_logic [Port]

fec_add out std_logic_vector ( 3 downto 0 ) [Port]

fec_add_dcs in std_logic_vector ( 3 downto 0 ) [Port]

fec_add_id in std_logic_vector ( 3 downto 0 ) [Port]

ieee library [Library]

ih_busy in std_logic [Port]

rnw out std_logic [Port]

rnw_dcs in std_logic [Port]

rnw_id in std_logic [Port]

std_logic_1164 package [Package]

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The documentation for this class was generated from the following file:

• msmodule/msm_lsc_core/msm_mux_signals/msm_mux_signals.vhd