addib_i | rtl | [Signal] |
bcast_i | rtl | [Signal] |
bcdata_i | rtl | [Signal] |
bcdata_id_i | rtl | [Signal] |
bcreg_add_i | rtl | [Signal] |
bcreg_add_id_i | rtl | [Signal] |
branch_i | rtl | [Signal] |
branch_id_i | rtl | [Signal] |
byte_i | rtl | [Signal] |
cnt_rx_i | rtl | [Signal] |
csr1_i | rtl | [Signal] |
data_fbc_i | rtl | [Signal] |
data_result_i | rtl | [Signal] |
data_valid_i | rtl | [Signal] |
dataresult_fsc_i | rtl | [Signal] |
error_i | rtl | [Signal] |
exec_i | rtl | [Signal] |
exec_id_i | rtl | [Signal] |
fec_add_i | rtl | [Signal] |
fec_add_id_i | rtl | [Signal] |
icode_i | rtl | [Signal] |
ih_busy_i | rtl | [Signal] |
instr_builder_1 | rtl | [Component Instantiation] |
interrupt_driver_1 | rtl | [Component Instantiation] |
master_1 | rtl | [Component Instantiation] |
master_end_i | rtl | [Signal] |
mux_signals_1 | rtl | [Component Instantiation] |
new_data_i | rtl | [Signal] |
read_i | rtl | [Signal] |
ready_i | rtl | [Signal] |
rnw_i | rtl | [Signal] |
rnw_id_i | rtl | [Signal] |
rwn_i | rtl | [Signal] |
sc_signals_1 | rtl | [Component Instantiation] |
scl_i | rtl | [Signal] |
sda_in_i | rtl | [Signal] |
seq_active_i | rtl | [Signal] |
sequencer_rcu_1 | rtl | [Component Instantiation] |
start_i | rtl | [Signal] |
stop_i | rtl | [Signal] |
word_i | rtl | [Signal] |
write_i | rtl | [Signal] |