rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
p_errors	( clk2 , rstb )
Signals
done_i	std_logic
cs_i	std_logic
chrdo_i	std_logic
valid_i	std_logic
load_i	std_logic
exec_i	std_logic
loadcs_i	std_logic
en1_i	std_logic
ackn_i	std_logic
en2_i	std_logic
waitst_i	std_logic
h_abt_i	std_logic
h_err_i	std_logic
add_r_i	std_logic_vector ( 19 downto 0 )
write_r_i	std_logic
rg_rd_i	std_logic
rg_wr_i	std_logic
push_i	std_logic
pop_i	std_logic
swtrg_i	std_logic
trc_clr_i	std_logic
err_clr_i	std_logic
wr_bsl_i	std_logic
rd_bsl_i	std_logic
bcast_i	std_logic
instr_err_i	std_logic
par_err_i	std_logic
trg_r_i	std_logic
l2y_r_i	std_logic
hwtrg_i	std_logic
csr_sel_i	std_logic_vector ( 4 downto 0 )
by0_i	std_logic
by1_i	std_logic
by2_i	std_logic
by3_i	std_logic
by4_i	std_logic
by5_i	std_logic
x0_i	std_logic
x1_i	std_logic
x2_i	std_logic
x3_i	std_logic
x4_i	std_logic
x5_i	std_logic
Component Instantiations
i_ctrl	intctrl <Entity intctrl>
i_dec	intdec <Entity intdec>
i_bus	busint <Entity busint>
i_exec	intexec <Entity intexec>
i_sync0	sync21 <Entity sync21>
i_sync1	sync21 <Entity sync21>
i_sync2	sync21 <Entity sync21>
i_sync3	sync21 <Entity sync21>
i_sync4	sync21 <Entity sync21>
i_sync5	sync21 <Entity sync21>

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Member Function Documentation

[Process]

p_errors		( clk2 ,
		rstb )

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Member Data Documentation

ackn_i std_logic [Signal]

add_r_i std_logic_vector ( 19 downto 0 ) [Signal]

bcast_i std_logic [Signal]

by0_i std_logic [Signal]

by1_i std_logic [Signal]

by2_i std_logic [Signal]

by3_i std_logic [Signal]

by4_i std_logic [Signal]

by5_i std_logic [Signal]

chrdo_i std_logic [Signal]

cs_i std_logic [Signal]

csr_sel_i std_logic_vector ( 4 downto 0 ) [Signal]

done_i std_logic [Signal]

en1_i std_logic [Signal]

en2_i std_logic [Signal]

err_clr_i std_logic [Signal]

exec_i std_logic [Signal]

h_abt_i std_logic [Signal]

h_err_i std_logic [Signal]

hwtrg_i std_logic [Signal]

i_bus busint [Component Instantiation]

i_ctrl intctrl [Component Instantiation]

i_dec intdec [Component Instantiation]

i_exec intexec [Component Instantiation]

i_sync0 sync21 [Component Instantiation]

i_sync1 sync21 [Component Instantiation]

i_sync2 sync21 [Component Instantiation]

i_sync3 sync21 [Component Instantiation]

i_sync4 sync21 [Component Instantiation]

i_sync5 sync21 [Component Instantiation]

instr_err_i std_logic [Signal]

l2y_r_i std_logic [Signal]

load_i std_logic [Signal]

loadcs_i std_logic [Signal]

par_err_i std_logic [Signal]

pop_i std_logic [Signal]

push_i std_logic [Signal]

rd_bsl_i std_logic [Signal]

rg_rd_i std_logic [Signal]

rg_wr_i std_logic [Signal]

swtrg_i std_logic [Signal]

trc_clr_i std_logic [Signal]

trg_r_i std_logic [Signal]

valid_i std_logic [Signal]

waitst_i std_logic [Signal]

wr_bsl_i std_logic [Signal]

write_r_i std_logic [Signal]

x0_i std_logic [Signal]

x1_i std_logic [Signal]

x2_i std_logic [Signal]

x3_i std_logic [Signal]

x4_i std_logic [Signal]

x5_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• altro/interface.vhd