| ackn_i | rtl | [Signal] |
| add_r_i | rtl | [Signal] |
| bcast_i | rtl | [Signal] |
| by0_i | rtl | [Signal] |
| by1_i | rtl | [Signal] |
| by2_i | rtl | [Signal] |
| by3_i | rtl | [Signal] |
| by4_i | rtl | [Signal] |
| by5_i | rtl | [Signal] |
| chrdo_i | rtl | [Signal] |
| cs_i | rtl | [Signal] |
| csr_sel_i | rtl | [Signal] |
| done_i | rtl | [Signal] |
| en1_i | rtl | [Signal] |
| en2_i | rtl | [Signal] |
| err_clr_i | rtl | [Signal] |
| exec_i | rtl | [Signal] |
| h_abt_i | rtl | [Signal] |
| h_err_i | rtl | [Signal] |
| hwtrg_i | rtl | [Signal] |
| i_bus | rtl | [Component Instantiation] |
| i_ctrl | rtl | [Component Instantiation] |
| i_dec | rtl | [Component Instantiation] |
| i_exec | rtl | [Component Instantiation] |
| i_sync0 | rtl | [Component Instantiation] |
| i_sync1 | rtl | [Component Instantiation] |
| i_sync2 | rtl | [Component Instantiation] |
| i_sync3 | rtl | [Component Instantiation] |
| i_sync4 | rtl | [Component Instantiation] |
| i_sync5 | rtl | [Component Instantiation] |
| instr_err_i | rtl | [Signal] |
| l2y_r_i | rtl | [Signal] |
| load_i | rtl | [Signal] |
| loadcs_i | rtl | [Signal] |
| p_errors(clk2, rstb) | rtl | [Process] |
| par_err_i | rtl | [Signal] |
| pop_i | rtl | [Signal] |
| push_i | rtl | [Signal] |
| rd_bsl_i | rtl | [Signal] |
| rg_rd_i | rtl | [Signal] |
| rg_wr_i | rtl | [Signal] |
| swtrg_i | rtl | [Signal] |
| trc_clr_i | rtl | [Signal] |
| trg_r_i | rtl | [Signal] |
| valid_i | rtl | [Signal] |
| waitst_i | rtl | [Signal] |
| wr_bsl_i | rtl | [Signal] |
| write_r_i | rtl | [Signal] |
| x0_i | rtl | [Signal] |
| x1_i | rtl | [Signal] |
| x2_i | rtl | [Signal] |
| x3_i | rtl | [Signal] |
| x4_i | rtl | [Signal] |
| x5_i | rtl | [Signal] |
1.6.2-20100208