intdec Entity Reference
[Model of ALTRO chip]
Inheritance diagram for intdec:
Collaboration diagram for intdec:
Architectures | |
| rtl | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
Ports | |
| add | in std_logic_vector ( 19 downto 0 ) |
| address | |
| wrt | in std_logic |
| write flag | |
| cs | in std_logic |
| Card select. | |
| valid | out std_logic |
| Valid instr. | |
| chrdo | out std_logic |
| channel readout | |
| rg_wr | out std_logic |
| write pointer | |
| rg_rd | out std_logic |
| read pointer | |
| push | out std_logic |
| Push it. | |
| pop | out std_logic |
| Pop it. | |
| swtrg | out std_logic |
| software trigger | |
| trc_clr | out std_logic |
| trigger counter clr | |
| err_clr | out std_logic |
| Error clear;. | |
| wr_bsl | out std_logic |
| Write base-line. | |
| rd_bsl | out std_logic |
| Read base-line. | |
| bcast | out std_logic |
| broadcast flag | |
| chadd | out std_logic_vector ( 3 downto 0 ) |
| channel address | |
| csr_sel | out std_logic_vector ( 4 downto 0 ) |
| Selected config. | |
| instr_err | out std_logic |
| Instruction error. | |
| par_err | out std_logic |
| Parity error. | |
Detailed Description
Decode the bus signals
Member Data Documentation
add in std_logic_vector ( 19 downto 0 ) [Port] |
address
bcast out std_logic [Port] |
broadcast flag
chadd out std_logic_vector ( 3 downto 0 ) [Port] |
channel address
chrdo out std_logic [Port] |
channel readout
cs in std_logic [Port] |
Card select.
csr_sel out std_logic_vector ( 4 downto 0 ) [Port] |
Selected config.
err_clr out std_logic [Port] |
Error clear;.
ieee library [Library] |
instr_err out std_logic [Port] |
Instruction error.
par_err out std_logic [Port] |
Parity error.
pop out std_logic [Port] |
Pop it.
push out std_logic [Port] |
Push it.
rd_bsl out std_logic [Port] |
Read base-line.
rg_rd out std_logic [Port] |
read pointer
rg_wr out std_logic [Port] |
write pointer
std_logic_1164 package [Package] |
swtrg out std_logic [Port] |
software trigger
trc_clr out std_logic [Port] |
trigger counter clr
valid out std_logic [Port] |
Valid instr.
wr_bsl out std_logic [Port] |
Write base-line.
wrt in std_logic [Port] |
write flag
The documentation for this class was generated from the following file:
- altro/intdec.vhd
