rtl Architecture Reference
[Model of ALTRO chip]

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Signals
w1_i	std_logic
w2_i	std_logic
w3_i	std_logic
w4_i	std_logic
bcast_rd_err_i	std_logic
bcast_err_i	std_logic
bcast_err2_i	std_logic
bcast_err3_i	std_logic
reg_err_i	std_logic
bank1_err_i	std_logic
bank2_err_i	std_logic
bank3_err_i	std_logic
bank0_sel_i	std_logic
bank1_sel_i	std_logic
bank2_sel_i	std_logic
bank3_sel_i	std_logic
read_i	std_logic
reg_err_new_i	std_logic
instr_err_i	std_logic
par_err_i	std_logic
csr_sel_i	std_logic_vector ( 4 downto 0 )
bcast_i	std_logic
valid_i	std_logic

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Detailed Description

Decode the bus signals

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Member Data Documentation

bank0_sel_i std_logic [Signal]

bank1_err_i std_logic [Signal]

bank1_sel_i std_logic [Signal]

bank2_err_i std_logic [Signal]

bank2_sel_i std_logic [Signal]

bank3_err_i std_logic [Signal]

bank3_sel_i std_logic [Signal]

bcast_err2_i std_logic [Signal]

bcast_err3_i std_logic [Signal]

bcast_err_i std_logic [Signal]

bcast_i std_logic [Signal]

bcast_rd_err_i std_logic [Signal]

csr_sel_i std_logic_vector ( 4 downto 0 ) [Signal]

instr_err_i std_logic [Signal]

par_err_i std_logic [Signal]

read_i std_logic [Signal]

reg_err_i std_logic [Signal]

reg_err_new_i std_logic [Signal]

valid_i std_logic [Signal]

w1_i std_logic [Signal]

w2_i std_logic [Signal]

w3_i std_logic [Signal]

w4_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• altro/intdec.vhd