sync21 Entity Reference
[Model of ALTRO chip]

Inheritance diagram for sync21:

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Collaboration diagram for sync21:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
Ports
x2	in std_logic
	Input.
clk	in std_logic
	clock
clk2	in std_logic
	clock
rstb	in std_logic
	reset
x1	out std_logic
	output
busyb	out std_logic
	Busy.

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Detailed Description

Syncronise x2 to clocks clk and clk2

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Member Data Documentation

busyb out std_logic [Port]

Busy.

clk in std_logic [Port]

clock

clk2 in std_logic [Port]

clock

ieee library [Library]

rstb in std_logic [Port]

reset

std_logic_1164 package [Package]

x1 out std_logic [Port]

output

x2 in std_logic [Port]

Input.

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The documentation for this class was generated from the following file:

• altro/sync21.vhd