rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Signals
sel_add_i	std_logic
clear_add_i	std_logic
enable_add_i	std_logic
sda_add_i	std_logic
for_us_i	std_logic
sel_rx_i	std_logic
clear_rx_i	std_logic
enable_rx_i	std_logic
reg_add_rx_i	std_logic_vector ( 6 downto 0 )
we_rx_i	std_logic
sda_rx_i	std_logic
ierr_rx_i	std_logic
sel_tx_i	std_logic
clear_tx_i	std_logic
enable_tx_i	std_logic
load_tx_i	std_logic
reg_add_tx_i	std_logic_vector ( 6 downto 0 )
sda_tx_i	std_logic
ierr_tx_i	std_logic
clear_i	std_logic
enable_i	std_logic
load_i	std_logic
cnt_8_i	std_logic
data_ser_in_i	std_logic
data_par_in_i	std_logic_vector ( 7 downto 0 )
data_par_out_i	std_logic_vector ( 7 downto 0 )
finish_tx_i	std_logic
finish_rx_i	std_logic
en_fec_tx_i	std_logic
en_fec_rx_i	std_logic
bcast_i	std_logic
state_dec_i	std_logic_vector ( 3 downto 0 )
state_rx_i	std_logic_vector ( 2 downto 0 )
state_tx_i	std_logic_vector ( 3 downto 0 )
Component Instantiations
serial	serializer_bc <Entity serializer_bc>
decoder	fec_address <Entity fec_address>
transmitter	slave_tx <Entity slave_tx>
reciever	slave_rx <Entity slave_rx>
selector	sel_signals <Entity sel_signals>

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Member Data Documentation

bcast_i std_logic [Signal]

clear_add_i std_logic [Signal]

clear_i std_logic [Signal]

clear_rx_i std_logic [Signal]

clear_tx_i std_logic [Signal]

cnt_8_i std_logic [Signal]

data_par_in_i std_logic_vector ( 7 downto 0 ) [Signal]

data_par_out_i std_logic_vector ( 7 downto 0 ) [Signal]

data_ser_in_i std_logic [Signal]

decoder fec_address [Component Instantiation]

en_fec_rx_i std_logic [Signal]

en_fec_tx_i std_logic [Signal]

enable_add_i std_logic [Signal]

enable_i std_logic [Signal]

enable_rx_i std_logic [Signal]

enable_tx_i std_logic [Signal]

finish_rx_i std_logic [Signal]

finish_tx_i std_logic [Signal]

for_us_i std_logic [Signal]

ierr_rx_i std_logic [Signal]

ierr_tx_i std_logic [Signal]

load_i std_logic [Signal]

load_tx_i std_logic [Signal]

reciever slave_rx [Component Instantiation]

reg_add_rx_i std_logic_vector ( 6 downto 0 ) [Signal]

reg_add_tx_i std_logic_vector ( 6 downto 0 ) [Signal]

sda_add_i std_logic [Signal]

sda_rx_i std_logic [Signal]

sda_tx_i std_logic [Signal]

sel_add_i std_logic [Signal]

sel_rx_i std_logic [Signal]

sel_tx_i std_logic [Signal]

selector sel_signals [Component Instantiation]

serial serializer_bc [Component Instantiation]

state_dec_i std_logic_vector ( 3 downto 0 ) [Signal]

state_rx_i std_logic_vector ( 2 downto 0 ) [Signal]

state_tx_i std_logic_vector ( 3 downto 0 ) [Signal]

transmitter slave_tx [Component Instantiation]

we_rx_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• bc/bc_core/slave/slave.vhd