slave_tx Entity Reference

Inheritance diagram for slave_tx:

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Collaboration diagram for slave_tx:

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List of all members.

Architectures
rtl	Architecture
rtl2	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
register_config	Package <register_config>
Ports
clk	in std_logic
rstb	in std_logic
bc_rst	in std_logic
csr1_clr	in std_logic
cnt_8	in std_logic
data_par_in	in std_logic_vector ( 7 downto 0 )
data_ser	in std_logic
data_tx	in std_logic_vector ( 15 downto 0 )
en_fec_tx	in std_logic
sda_in	in std_logic
scl	in std_logic
bcast	in std_logic
clear	out std_logic
data_par_out	out std_logic_vector ( 7 downto 0 )
enable	out std_logic
load	out std_logic
finish_tx	out std_logic
sda_out	out std_logic
reg_add	out std_logic_vector ( 6 downto 0 )
sel_tx	out std_logic
ierr_tx	out std_logic
state	out std_logic_vector ( 3 downto 0 )

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Member Data Documentation

bc_rst in std_logic [Port]

bcast in std_logic [Port]

clear out std_logic [Port]

clk in std_logic [Port]

cnt_8 in std_logic [Port]

csr1_clr in std_logic [Port]

data_par_in in std_logic_vector ( 7 downto 0 ) [Port]

data_par_out out std_logic_vector ( 7 downto 0 ) [Port]

data_ser in std_logic [Port]

data_tx in std_logic_vector ( 15 downto 0 ) [Port]

en_fec_tx in std_logic [Port]

enable out std_logic [Port]

finish_tx out std_logic [Port]

ieee library [Library]

ierr_tx out std_logic [Port]

load out std_logic [Port]

numeric_std package [Package]

reg_add out std_logic_vector ( 6 downto 0 ) [Port]

register_config package [Package]

rstb in std_logic [Port]

scl in std_logic [Port]

sda_in in std_logic [Port]

sda_out out std_logic [Port]

sel_tx out std_logic [Port]

state out std_logic_vector ( 3 downto 0 ) [Port]

std_logic_1164 package [Package]

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The documentation for this class was generated from the following file:

• bc/bc_core/slave/slave_tx/slave_tx.vhd