rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
next_state	( clk , rstb )
slave_tx_fsm	( st_i , en_fec_tx , scl , sda_in , cnt_8 , data_ser , ierr_tx_i )
counter	( clk , rstb )
output	( clk , rstb )
Constants
ST_idle	std_logic_vector ( 3 downto 0 ) := " 0000 "
ST_start	std_logic_vector ( 3 downto 0 ) := " 0001 "
ST_wait_add	std_logic_vector ( 3 downto 0 ) := " 0010 "
ST_store_add	std_logic_vector ( 3 downto 0 ) := " 0011 "
ST_ack_1	std_logic_vector ( 3 downto 0 ) := " 0100 "
ST_ack_2	std_logic_vector ( 3 downto 0 ) := " 0101 "
ST_load_1	std_logic_vector ( 3 downto 0 ) := " 0110 "
ST_load_2	std_logic_vector ( 3 downto 0 ) := " 0111 "
ST_wait_dt	std_logic_vector ( 3 downto 0 ) := " 1000 "
ST_store_dt	std_logic_vector ( 3 downto 0 ) := " 1001 "
ST_ack_master_1	std_logic_vector ( 3 downto 0 ) := " 1010 "
ST_ack_master_2	std_logic_vector ( 3 downto 0 ) := " 1011 "
ST_wait_stop_1	std_logic_vector ( 3 downto 0 ) := " 1100 "
ST_wait_stop_2	std_logic_vector ( 3 downto 0 ) := " 1101 "
ST_wait_stop_3	std_logic_vector ( 3 downto 0 ) := " 1110 "
ST_preload	std_logic_vector ( 3 downto 0 ) := " 1111 "
Types
state_t	( idle , start , wait_add , store_add , ack_1 , ack_2 , load_1 , load_2 , wait_dt , store_dt , ack_master_1 , ack_master_2 , wait_stop_1 , wait_stop_2 , wait_stop_3 , preload )
Signals
st_i	state_t
nx_st_i	state_t
clr_cnt_i	std_logic
en_cnt_i	std_logic
en_reg_i	std_logic
cnt_i	unsigned ( 0 downto 0 )
ierr_tx_i	std_logic
reg_add_i	integer range 0 to NUM_REG -1
not_sc_i	std_logic
not_bcast_i	std_logic

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Member Function Documentation

[Process]

counter		( clk ,
		rstb )

[Process]

next_state		( clk ,
		rstb )

[Process]

output		( clk ,
		rstb )

[Process]

slave_tx_fsm		( st_i ,
		en_fec_tx ,
		scl ,
		sda_in ,
		cnt_8 ,
		data_ser ,
		ierr_tx_i )

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Member Data Documentation

clr_cnt_i std_logic [Signal]

cnt_i unsigned ( 0 downto 0 ) [Signal]

en_cnt_i std_logic [Signal]

en_reg_i std_logic [Signal]

ierr_tx_i std_logic [Signal]

not_bcast_i std_logic [Signal]

not_sc_i std_logic [Signal]

nx_st_i state_t [Signal]

reg_add_i integer range 0 to NUM_REG -1 [Signal]

ST_ack_1 std_logic_vector ( 3 downto 0 ) := " 0100 " [Constant]

ST_ack_2 std_logic_vector ( 3 downto 0 ) := " 0101 " [Constant]

ST_ack_master_1 std_logic_vector ( 3 downto 0 ) := " 1010 " [Constant]

ST_ack_master_2 std_logic_vector ( 3 downto 0 ) := " 1011 " [Constant]

st_i state_t [Signal]

ST_idle std_logic_vector ( 3 downto 0 ) := " 0000 " [Constant]

ST_load_1 std_logic_vector ( 3 downto 0 ) := " 0110 " [Constant]

ST_load_2 std_logic_vector ( 3 downto 0 ) := " 0111 " [Constant]

ST_preload std_logic_vector ( 3 downto 0 ) := " 1111 " [Constant]

ST_start std_logic_vector ( 3 downto 0 ) := " 0001 " [Constant]

ST_store_add std_logic_vector ( 3 downto 0 ) := " 0011 " [Constant]

ST_store_dt std_logic_vector ( 3 downto 0 ) := " 1001 " [Constant]

ST_wait_add std_logic_vector ( 3 downto 0 ) := " 0010 " [Constant]

ST_wait_dt std_logic_vector ( 3 downto 0 ) := " 1000 " [Constant]

ST_wait_stop_1 std_logic_vector ( 3 downto 0 ) := " 1100 " [Constant]

ST_wait_stop_2 std_logic_vector ( 3 downto 0 ) := " 1101 " [Constant]

ST_wait_stop_3 std_logic_vector ( 3 downto 0 ) := " 1110 " [Constant]

state_t ( idle , start , wait_add , store_add , ack_1 , ack_2 , load_1 , load_2 , wait_dt , store_dt , ack_master_1 , ack_master_2 , wait_stop_1 , wait_stop_2 , wait_stop_3 , preload ) [Type]

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The documentation for this class was generated from the following file:

• bc/bc_core/slave/slave_tx/slave_tx.vhd