clr_cnt_i | rtl | [Signal] |
cnt_i | rtl | [Signal] |
counter(clk, rstb) | rtl | [Process] |
en_cnt_i | rtl | [Signal] |
en_reg_i | rtl | [Signal] |
ierr_tx_i | rtl | [Signal] |
next_state(clk, rstb) | rtl | [Process] |
not_bcast_i | rtl | [Signal] |
not_sc_i | rtl | [Signal] |
nx_st_i | rtl | [Signal] |
output(clk, rstb) | rtl | [Process] |
reg_add_i | rtl | [Signal] |
slave_tx_fsm(st_i, en_fec_tx, scl, sda_in, cnt_8,data_ser, ierr_tx_i) | rtl | [Process] |
ST_ack_1 | rtl | [Constant] |
ST_ack_2 | rtl | [Constant] |
ST_ack_master_1 | rtl | [Constant] |
ST_ack_master_2 | rtl | [Constant] |
st_i | rtl | [Signal] |
ST_idle | rtl | [Constant] |
ST_load_1 | rtl | [Constant] |
ST_load_2 | rtl | [Constant] |
ST_preload | rtl | [Constant] |
ST_start | rtl | [Constant] |
ST_store_add | rtl | [Constant] |
ST_store_dt | rtl | [Constant] |
ST_wait_add | rtl | [Constant] |
ST_wait_dt | rtl | [Constant] |
ST_wait_stop_1 | rtl | [Constant] |
ST_wait_stop_2 | rtl | [Constant] |
ST_wait_stop_3 | rtl | [Constant] |
state_t | rtl | [Type] |