slave_rx Entity Reference

Inheritance diagram for slave_rx:

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Collaboration diagram for slave_rx:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
register_config	Package <register_config>
Ports
clk	in std_logic
rstb	in std_logic
bc_rst	in std_logic
csr1_clr	in std_logic
cnt_8	in std_logic
en_fec_rx	in std_logic
data_par_in	in std_logic_vector ( 7 downto 0 )
sda_in	in std_logic
scl	in std_logic
clear	out std_logic
enable	out std_logic
data	out std_logic_vector ( 15 downto 0 )
reg_add	out std_logic_vector ( 6 downto 0 )
sda_out	out std_logic
sel_rx	out std_logic
finish_rx	out std_logic
we	out std_logic
ierr_rx	out std_logic
state	out std_logic_vector ( 2 downto 0 )

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Member Data Documentation

bc_rst in std_logic [Port]

clear out std_logic [Port]

clk in std_logic [Port]

cnt_8 in std_logic [Port]

csr1_clr in std_logic [Port]

data out std_logic_vector ( 15 downto 0 ) [Port]

data_par_in in std_logic_vector ( 7 downto 0 ) [Port]

en_fec_rx in std_logic [Port]

enable out std_logic [Port]

finish_rx out std_logic [Port]

ieee library [Library]

ierr_rx out std_logic [Port]

numeric_std package [Package]

reg_add out std_logic_vector ( 6 downto 0 ) [Port]

register_config package [Package]

rstb in std_logic [Port]

scl in std_logic [Port]

sda_in in std_logic [Port]

sda_out out std_logic [Port]

sel_rx out std_logic [Port]

state out std_logic_vector ( 2 downto 0 ) [Port]

std_logic_1164 package [Package]

we out std_logic [Port]

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The documentation for this class was generated from the following file:

• bc/bc_core/slave/slave_rx/slave_rx.vhd