rtl Architecture Reference

Inheritance diagram for rtl:

Collaboration diagram for rtl:

Processes
update_state	( clk , rstb )
rx_fsm	( st_i , scl , sda_in , en_fec_rx , cnt_8 , ierr_rx_i )
counter	( clk , rstb )
output	( clk , rstb )
Constants
ST_IDLE	std_logic_vector ( 2 downto 0 ) := " 000 "
ST_START	std_logic_vector ( 2 downto 0 ) := " 001 "
ST_WAIT_DT	std_logic_vector ( 2 downto 0 ) := " 010 "
ST_STORE_DT	std_logic_vector ( 2 downto 0 ) := " 011 "
ST_ACK_1	std_logic_vector ( 2 downto 0 ) := " 100 "
ST_ACK_2	std_logic_vector ( 2 downto 0 ) := " 101 "
ST_WAIT_STOP	std_logic_vector ( 2 downto 0 ) := " 110 "
Types
state_t	( idle , start , wait_dt , store_dt , ack_1 , ack_2 , wait_stop )
Signals
st_i	state_t
nx_st_i	state_t
ierr_rx_i	std_logic
clr_cnt_i	std_logic
en_cnt_i	std_logic
en_reg_i	std_logic
cnt_i	unsigned ( 1 downto 0 ) := ( others = > ' 0 ' )
reg_add_i	integer range 0 to NUM_REG -1 := 0

Member Function Documentation

[Process]

counter		( clk ,
		rstb )

[Process]

output		( clk ,
		rstb )

[Process]

[Process]

update_state		( clk ,
		rstb )

clr_cnt_i std_logic [Signal]

cnt_i unsigned ( 1 downto 0 ) := ( others = > ' 0 ' ) [Signal]

en_cnt_i std_logic [Signal]

en_reg_i std_logic [Signal]

ierr_rx_i std_logic [Signal]

nx_st_i state_t [Signal]

reg_add_i integer range 0 to NUM_REG -1 := 0 [Signal]

ST_ACK_1 std_logic_vector ( 2 downto 0 ) := " 100 " [Constant]

ST_ACK_2 std_logic_vector ( 2 downto 0 ) := " 101 " [Constant]

st_i state_t [Signal]

ST_IDLE std_logic_vector ( 2 downto 0 ) := " 000 " [Constant]

ST_START std_logic_vector ( 2 downto 0 ) := " 001 " [Constant]

ST_STORE_DT std_logic_vector ( 2 downto 0 ) := " 011 " [Constant]

ST_WAIT_DT std_logic_vector ( 2 downto 0 ) := " 010 " [Constant]

ST_WAIT_STOP std_logic_vector ( 2 downto 0 ) := " 110 " [Constant]

state_t ( idle , start , wait_dt , store_dt , ack_1 , ack_2 , wait_stop ) [Type]

The documentation for this class was generated from the following file: