clr_cnt_i | rtl | [Signal] |
cnt_i | rtl | [Signal] |
counter(clk, rstb) | rtl | [Process] |
en_cnt_i | rtl | [Signal] |
en_reg_i | rtl | [Signal] |
ierr_rx_i | rtl | [Signal] |
nx_st_i | rtl | [Signal] |
output(clk, rstb) | rtl | [Process] |
reg_add_i | rtl | [Signal] |
rx_fsm(st_i, scl, sda_in, en_fec_rx, cnt_8, ierr_rx_i) | rtl | [Process] |
ST_ACK_1 | rtl | [Constant] |
ST_ACK_2 | rtl | [Constant] |
st_i | rtl | [Signal] |
ST_IDLE | rtl | [Constant] |
ST_START | rtl | [Constant] |
ST_STORE_DT | rtl | [Constant] |
ST_WAIT_DT | rtl | [Constant] |
ST_WAIT_STOP | rtl | [Constant] |
state_t | rtl | [Type] |
update_state(clk, rstb) | rtl | [Process] |