sel_signals Entity Reference

Inheritance diagram for sel_signals:

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Collaboration diagram for sel_signals:

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List of all members.

Architectures
rtl_async	Architecture
rtl_clocked	Architecture
Libraries
ieee
Packages
std_logic_1164
Ports
clk	in std_logic
rstb	in std_logic
sel_add	in std_logic
clear_add	in std_logic
enable_add	in std_logic
sda_add	in std_logic
for_us	in std_logic
sel_rx	in std_logic
clear_rx	in std_logic
enable_rx	in std_logic
reg_add_rx	in std_logic_vector ( 6 downto 0 )
we_rx	in std_logic
sda_rx	in std_logic
ierr_rx	in std_logic
sel_tx	in std_logic
clear_tx	in std_logic
enable_tx	in std_logic
load_tx	in std_logic
reg_add_tx	in std_logic_vector ( 6 downto 0 )
sda_tx	in std_logic
ierr_tx	in std_logic
clear	out std_logic
enable	out std_logic
load	out std_logic
reg_add	out std_logic_vector ( 6 downto 0 )
sda	out std_logic
we	out std_logic
ierr_sc	out std_logic

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Member Data Documentation

clear out std_logic [Port]

clear_add in std_logic [Port]

clear_rx in std_logic [Port]

clear_tx in std_logic [Port]

clk in std_logic [Port]

enable out std_logic [Port]

enable_add in std_logic [Port]

enable_rx in std_logic [Port]

enable_tx in std_logic [Port]

for_us in std_logic [Port]

ieee library [Library]

ierr_rx in std_logic [Port]

ierr_sc out std_logic [Port]

ierr_tx in std_logic [Port]

load out std_logic [Port]

load_tx in std_logic [Port]

reg_add out std_logic_vector ( 6 downto 0 ) [Port]

reg_add_rx in std_logic_vector ( 6 downto 0 ) [Port]

reg_add_tx in std_logic_vector ( 6 downto 0 ) [Port]

rstb in std_logic [Port]

sda out std_logic [Port]

sda_add in std_logic [Port]

sda_rx in std_logic [Port]

sda_tx in std_logic [Port]

sel_add in std_logic [Port]

sel_rx in std_logic [Port]

sel_tx in std_logic [Port]

std_logic_1164 package [Package]

we out std_logic [Port]

we_rx in std_logic [Port]

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The documentation for this class was generated from the following file:

• bc/bc_core/slave/sel_signals/sel_signals.vhd