rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
s_counter	( clk_scl_i , rstb )
count_2	( clk , rstb )
Signals
clk_scl_i	std_logic
clk_en_i	std_logic
cnt_2_i	std_logic_vector ( 1 downto 0 )
s_en_i	std_logic
en_2_i	std_logic
s_i	std_logic
width_i	std_logic
data_par_out_i	std_logic_vector ( 7 downto 0 )
master_ready_i	std_logic
data_valid_i	std_logic
clear_i	std_logic
load_i	std_logic
enable_i	std_logic
data_ser_out_i	std_logic
en_cnt_i	std_logic
data_ser_in_i	std_logic
sda_i	std_logic
sel_sda_in_i	std_logic
sel_sda_out_i	std_logic
sda_in_i	std_logic
valid_i	std_logic
scl_i	std_logic
en_data2_i	std_logic
en_tri2_i	std_logic
en_data1_i	std_logic
Component Instantiations
clock_scale	clock_scl <Entity clock_scl>
serialize	serializer <Entity serializer>
mst	master_sm <Entity master_sm>
decode	decoder <Entity decoder>
executor	exec <Entity exec>
sync_it	sync <Entity sync>

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Member Function Documentation

[Process]

count_2		( clk ,
		rstb )

[Process]

s_counter		( clk_scl_i ,
		rstb )

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Member Data Documentation

clear_i std_logic [Signal]

clk_en_i std_logic [Signal]

clk_scl_i std_logic [Signal]

clock_scale clock_scl [Component Instantiation]

cnt_2_i std_logic_vector ( 1 downto 0 ) [Signal]

data_par_out_i std_logic_vector ( 7 downto 0 ) [Signal]

data_ser_in_i std_logic [Signal]

data_ser_out_i std_logic [Signal]

data_valid_i std_logic [Signal]

decode decoder [Component Instantiation]

en_2_i std_logic [Signal]

en_cnt_i std_logic [Signal]

en_data1_i std_logic [Signal]

en_data2_i std_logic [Signal]

en_tri2_i std_logic [Signal]

enable_i std_logic [Signal]

executor exec [Component Instantiation]

load_i std_logic [Signal]

master_ready_i std_logic [Signal]

mst master_sm [Component Instantiation]

s_en_i std_logic [Signal]

s_i std_logic [Signal]

scl_i std_logic [Signal]

sda_i std_logic [Signal]

sda_in_i std_logic [Signal]

sel_sda_in_i std_logic [Signal]

sel_sda_out_i std_logic [Signal]

serialize serializer [Component Instantiation]

sync_it sync [Component Instantiation]

valid_i std_logic [Signal]

width_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• bc/bc_core/interface_adc/master/master.vhd