master_sm Entity Reference

Inheritance diagram for master_sm:

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Collaboration diagram for master_sm:

[legend]

List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
Ports
clk	in std_logic
clk_en	in std_logic
rstb	in std_logic
cnt_2	in std_logic_vector ( 1 downto 0 )
cnt_8	in std_logic
new_data	in std_logic
rw	in std_logic
sda_ser	in std_logic
start	in std_logic
stop	in std_logic
sda	in std_logic
width	in std_logic
clear	out std_logic
data_valid	out std_logic
en_cnt_2	out std_logic
enable	out std_logic
load	out std_logic
ready	out std_logic
s_en	out std_logic
scl	out std_logic
sda_in	out std_logic
sel_sda_in	out std_logic
sel_sda_out	out std_logic
valid	out std_logic
error	out std_logic
state	out std_logic_vector ( 4 downto 0 )

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Member Data Documentation

clear out std_logic [Port]

clk in std_logic [Port]

clk_en in std_logic [Port]

cnt_2 in std_logic_vector ( 1 downto 0 ) [Port]

cnt_8 in std_logic [Port]

data_valid out std_logic [Port]

en_cnt_2 out std_logic [Port]

enable out std_logic [Port]

error out std_logic [Port]

ieee library [Library]

load out std_logic [Port]

new_data in std_logic [Port]

ready out std_logic [Port]

rstb in std_logic [Port]

rw in std_logic [Port]

s_en out std_logic [Port]

scl out std_logic [Port]

sda in std_logic [Port]

sda_in out std_logic [Port]

sda_ser in std_logic [Port]

sel_sda_in out std_logic [Port]

sel_sda_out out std_logic [Port]

start in std_logic [Port]

state out std_logic_vector ( 4 downto 0 ) [Port]

std_logic_1164 package [Package]

stop in std_logic [Port]

valid out std_logic [Port]

width in std_logic [Port]

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The documentation for this class was generated from the following file:

• bc/bc_core/interface_adc/master/master_sm/master_sm.vhd