clear_i | rtl | [Signal] |
clk_en_i | rtl | [Signal] |
clk_scl_i | rtl | [Signal] |
clock_scale | rtl | [Component Instantiation] |
cnt_2_i | rtl | [Signal] |
count_2(clk, rstb) | rtl | [Process] |
data_par_out_i | rtl | [Signal] |
data_ser_in_i | rtl | [Signal] |
data_ser_out_i | rtl | [Signal] |
data_valid_i | rtl | [Signal] |
decode | rtl | [Component Instantiation] |
en_2_i | rtl | [Signal] |
en_cnt_i | rtl | [Signal] |
en_data1_i | rtl | [Signal] |
en_data2_i | rtl | [Signal] |
en_tri2_i | rtl | [Signal] |
enable_i | rtl | [Signal] |
executor | rtl | [Component Instantiation] |
load_i | rtl | [Signal] |
master_ready_i | rtl | [Signal] |
mst | rtl | [Component Instantiation] |
s_counter(clk_scl_i, rstb) | rtl | [Process] |
s_en_i | rtl | [Signal] |
s_i | rtl | [Signal] |
scl_i | rtl | [Signal] |
sda_i | rtl | [Signal] |
sda_in_i | rtl | [Signal] |
sel_sda_in_i | rtl | [Signal] |
sel_sda_out_i | rtl | [Signal] |
serialize | rtl | [Component Instantiation] |
sync_it | rtl | [Component Instantiation] |
valid_i | rtl | [Signal] |
width_i | rtl | [Signal] |