Architectures | |
rtl | Architecture |
Libraries | |
ieee | |
Packages | |
std_logic_1164 | |
Ports | |
clk | in std_logic |
rstb | in std_logic |
data | in std_logic_vector ( 7 downto 0 ) |
data_valid | in std_logic |
s | in std_logic |
width | in std_logic |
en_add | out std_logic |
out_reg | out std_logic_vector ( 15 downto 0 ) |
clk in std_logic [Port] |
data in std_logic_vector ( 7 downto 0 ) [Port] |
data_valid in std_logic [Port] |
en_add out std_logic [Port] |
ieee library [Library] |
out_reg out std_logic_vector ( 15 downto 0 ) [Port] |
rstb in std_logic [Port] |
s in std_logic [Port] |
std_logic_1164 package [Package] |
width in std_logic [Port] |