master Entity Reference

Inheritance diagram for master:

[legend]

Collaboration diagram for master:

[legend]

List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
sync_pack	Package <sync_pack>
exec_pack	Package <exec_pack>
clock_scl_pack	Package <clock_scl_pack>
decoder_pack	Package <decoder_pack>
serializer_pack	Package <serializer_pack>
master_sm_pack	Package <master_sm_pack>
Generics
MSCL_DIV	natural := 32
Ports
clk	in std_logic
rstb	in std_logic
data_par_in	in std_logic_vector ( 7 downto 0 )
new_data	in std_logic
rw	in std_logic
start	in std_logic
stop	in std_logic
width	out std_logic
en_add	out std_logic
data_adc	out std_logic_vector ( 15 downto 0 )
ready_seq	out std_logic
data_valid	out std_logic
error	out std_logic
s	out std_logic
scl	out std_logic
sda	inout std_logic
state	out std_logic_vector ( 4 downto 0 )

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Member Data Documentation

clk in std_logic [Port]

clock_scl_pack package [Package]

data_adc out std_logic_vector ( 15 downto 0 ) [Port]

data_par_in in std_logic_vector ( 7 downto 0 ) [Port]

data_valid out std_logic [Port]

decoder_pack package [Package]

en_add out std_logic [Port]

error out std_logic [Port]

exec_pack package [Package]

ieee library [Library]

master_sm_pack package [Package]

MSCL_DIV natural := 32 [Generic]

new_data in std_logic [Port]

numeric_std package [Package]

ready_seq out std_logic [Port]

rstb in std_logic [Port]

rw in std_logic [Port]

s out std_logic [Port]

scl out std_logic [Port]

sda inout std_logic [Port]

serializer_pack package [Package]

start in std_logic [Port]

state out std_logic_vector ( 4 downto 0 ) [Port]

std_logic_1164 package [Package]

stop in std_logic [Port]

sync_pack package [Package]

width out std_logic [Port]

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The documentation for this class was generated from the following file:

• bc/bc_core/interface_adc/master/master.vhd