clock_scl Entity Reference

Inheritance diagram for clock_scl:

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Collaboration diagram for clock_scl:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
Generics
DIV	integer := 32
Ports
clk	in std_logic
rstb	in std_logic
clk_scl	out std_logic
clk_en	out std_logic

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Member Data Documentation

clk in std_logic [Port]

clk_en out std_logic [Port]

clk_scl out std_logic [Port]

DIV integer := 32 [Generic]

ieee library [Library]

rstb in std_logic [Port]

std_logic_1164 package [Package]

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The documentation for this class was generated from the following file:

• bc/bc_core/interface_adc/master/clock_scl/clock_scl.vhd