rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Signals
add_al_i	std_logic_vector ( 6 downto 0 )
wr_bc_i	std_logic
bc_ackn_en_i	std_logic
valid_i	std_logic
lastst_al_i	std_logic
bcast_al_i	std_logic
ierr_al_i	std_logic
wadd_i	std_logic_vector ( 6 downto 0 )
wdata_i	std_logic_vector ( 15 downto 0 )
we_reg_i	std_logic
altro_sw_i	std_logic
missed_sclk_i	std_logic
par_error_i	std_logic
add_sc_i	std_logic_vector ( 6 downto 0 )
data_sc_i	std_logic_vector ( 15 downto 0 )
wr_sc_i	std_logic
bcast_sc_i	std_logic
ierr_sc_i	std_logic
slctr_i	std_logic
exec_i	std_logic
cnt_lat_i	std_logic
cnt_clr_i	std_logic
csr1_clr_i	std_logic
bc_rst_i	std_logic
st_cnv_i	std_logic
sc_evl_i	std_logic
evl_rdo_i	std_logic
st_tsm_i	std_logic
acq_rdo_i	std_logic
csr2_i	std_logic_vector ( 15 downto 0 )
csr3_i	std_logic_vector ( 15 downto 0 )
start_mon_i	std_logic
end_seq_i	std_logic
add_adc_i	std_logic_vector ( 4 downto 0 )
data_adc_i	std_logic_vector ( 15 downto 0 )
we_adc_i	std_logic
cnv_mode_i	std_logic
tsm_word_i	std_logic_vector ( 8 downto 0 )
us_ratio_i	std_logic_vector ( 15 downto 0 )
tsm_dec_en_i	std_logic
tsm_acqon_i	std_logic
tsm_isol_i	std_logic
tsm_out_i	std_logic_vector ( 7 downto 0 )
mtrsf_en_i	std_logic
mtrsf_i	std_logic
mdstb_i	std_logic
mdata_out_i	std_logic_vector ( 39 downto 0 )
rtrsf_en_i	std_logic
rtrsf_i	std_logic
rdstb_i	std_logic
rdata_out_i	std_logic_vector ( 39 downto 0 )
rmtrsf_en_i	std_logic
trsf_i	std_logic
dout_al_i	std_logic_vector ( 15 downto 0 )
dout_sc_i	std_logic_vector ( 15 downto 0 )
Component Instantiations
bus_interface	altrobusinterface <Entity altrobusinterface>
i2c_slave	slave <Entity slave>
decoder	interfacedec <Entity interfacedec>
monitors	interface_adc <Entity interface_adc>
regs	registers <Entity registers>
tsm_manager	tsm_man <Entity tsm_man>
evl_manager	evl_man <Entity evl_man>
out_multiplex	trsf_mux <Entity trsf_mux>
tsm_dec	tsm_decoder <Entity tsm_decoder>
al_sw_mask	altro_sw_mask_out <Entity altro_sw_mask_out>

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Member Data Documentation

acq_rdo_i std_logic [Signal]

add_adc_i std_logic_vector ( 4 downto 0 ) [Signal]

add_al_i std_logic_vector ( 6 downto 0 ) [Signal]

add_sc_i std_logic_vector ( 6 downto 0 ) [Signal]

al_sw_mask altro_sw_mask_out [Component Instantiation]

altro_sw_i std_logic [Signal]

bc_ackn_en_i std_logic [Signal]

bc_rst_i std_logic [Signal]

bcast_al_i std_logic [Signal]

bcast_sc_i std_logic [Signal]

bus_interface altrobusinterface [Component Instantiation]

cnt_clr_i std_logic [Signal]

cnt_lat_i std_logic [Signal]

cnv_mode_i std_logic [Signal]

csr1_clr_i std_logic [Signal]

csr2_i std_logic_vector ( 15 downto 0 ) [Signal]

csr3_i std_logic_vector ( 15 downto 0 ) [Signal]

data_adc_i std_logic_vector ( 15 downto 0 ) [Signal]

data_sc_i std_logic_vector ( 15 downto 0 ) [Signal]

decoder interfacedec [Component Instantiation]

dout_al_i std_logic_vector ( 15 downto 0 ) [Signal]

dout_sc_i std_logic_vector ( 15 downto 0 ) [Signal]

end_seq_i std_logic [Signal]

evl_manager evl_man [Component Instantiation]

evl_rdo_i std_logic [Signal]

exec_i std_logic [Signal]

i2c_slave slave [Component Instantiation]

ierr_al_i std_logic [Signal]

ierr_sc_i std_logic [Signal]

lastst_al_i std_logic [Signal]

mdata_out_i std_logic_vector ( 39 downto 0 ) [Signal]

mdstb_i std_logic [Signal]

missed_sclk_i std_logic [Signal]

monitors interface_adc [Component Instantiation]

mtrsf_en_i std_logic [Signal]

mtrsf_i std_logic [Signal]

out_multiplex trsf_mux [Component Instantiation]

par_error_i std_logic [Signal]

rdata_out_i std_logic_vector ( 39 downto 0 ) [Signal]

rdstb_i std_logic [Signal]

regs registers [Component Instantiation]

rmtrsf_en_i std_logic [Signal]

rtrsf_en_i std_logic [Signal]

rtrsf_i std_logic [Signal]

sc_evl_i std_logic [Signal]

slctr_i std_logic [Signal]

st_cnv_i std_logic [Signal]

st_tsm_i std_logic [Signal]

start_mon_i std_logic [Signal]

trsf_i std_logic [Signal]

tsm_acqon_i std_logic [Signal]

tsm_dec tsm_decoder [Component Instantiation]

tsm_dec_en_i std_logic [Signal]

tsm_isol_i std_logic [Signal]

tsm_manager tsm_man [Component Instantiation]

tsm_out_i std_logic_vector ( 7 downto 0 ) [Signal]

tsm_word_i std_logic_vector ( 8 downto 0 ) [Signal]

us_ratio_i std_logic_vector ( 15 downto 0 ) [Signal]

valid_i std_logic [Signal]

wadd_i std_logic_vector ( 6 downto 0 ) [Signal]

wdata_i std_logic_vector ( 15 downto 0 ) [Signal]

we_adc_i std_logic [Signal]

we_reg_i std_logic [Signal]

wr_bc_i std_logic [Signal]

wr_sc_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• bc/bc_core/bc_core.vhd