registers Entity Reference
Inheritance diagram for registers:
Collaboration diagram for registers:
Architectures | |
| rtl | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| registers_block_pack | Package <registers_block_pack> |
| counters_pack | Package <counters_pack> |
Ports | |
| clk | in std_logic |
| sclk | in std_logic |
| rstb | in std_logic |
| we | in std_logic |
| wadd | in std_logic_vector ( 6 downto 0 ) |
| wdata | in std_logic_vector ( 15 downto 0 ) |
| add_al | in std_logic_vector ( 6 downto 0 ) |
| add_sc | in std_logic_vector ( 6 downto 0 ) |
| dout_al | out std_logic_vector ( 15 downto 0 ) |
| dout_sc | out std_logic_vector ( 15 downto 0 ) |
| end_seq | in std_logic |
| we_adc | in std_logic |
| add_adc | in std_logic_vector ( 4 downto 0 ) |
| data_adc | in std_logic_vector ( 15 downto 0 ) |
| cnv_mode | out std_logic |
| fmdd_stat | in std_logic_vector ( 15 downto 0 ) |
| l0 | in std_logic |
| l1_trg | in std_logic |
| l2_trg | in std_logic |
| dstb | in std_logic |
| al_trsf | in std_logic |
| par_error | in std_logic |
| paps_error | in std_logic |
| alps_error | in std_logic |
| ierr_sc | in std_logic |
| ierr_al | in std_logic |
| al_error | in std_logic |
| bc_rst | in std_logic |
| csr1_clr | in std_logic |
| cnt_lat | in std_logic |
| cnt_clr | in std_logic |
| st_cnv | in std_logic |
| hadd | in std_logic_vector ( 4 downto 0 ) |
| missed_sclk | out std_logic |
| bc_int | out std_logic |
| bc_error | out std_logic |
| csr2 | out std_logic_vector ( 15 downto 0 ) |
| csr3 | out std_logic_vector ( 15 downto 0 ) |
| tsm_word | out std_logic_vector ( 8 downto 0 ) |
| us_ratio | out std_logic_vector ( 15 downto 0 ) |
| hold_wait | out std_logic_vector ( 15 downto 0 ) |
| l1_timeout | out std_logic_vector ( 15 downto 0 ) |
| l2_timeout | out std_logic_vector ( 15 downto 0 ) |
| shift_div | out std_logic_vector ( 15 downto 0 ) |
| strips | out std_logic_vector ( 15 downto 0 ) |
| cal_level | out std_logic_vector ( 15 downto 0 ) |
| shape_bias | out std_logic_vector ( 15 downto 0 ) |
| vfs | out std_logic_vector ( 15 downto 0 ) |
| vfp | out std_logic_vector ( 15 downto 0 ) |
| sample_div | out std_logic_vector ( 15 downto 0 ) |
| fmdd_cmd | out std_logic_vector ( 15 downto 0 ) |
| cal_iter | out std_logic_vector ( 15 downto 0 ) |
| mebs | out std_logic_vector ( 4 downto 0 ) |
| meb_cnt | in std_logic_vector ( 3 downto 0 ) |
| cal_delay | out std_logic_vector ( 15 downto 0 ) |
Member Data Documentation
add_adc in std_logic_vector ( 4 downto 0 ) [Port] |
add_al in std_logic_vector ( 6 downto 0 ) [Port] |
add_sc in std_logic_vector ( 6 downto 0 ) [Port] |
al_error in std_logic [Port] |
al_trsf in std_logic [Port] |
alps_error in std_logic [Port] |
bc_error out std_logic [Port] |
bc_int out std_logic [Port] |
bc_rst in std_logic [Port] |
cal_delay out std_logic_vector ( 15 downto 0 ) [Port] |
cal_iter out std_logic_vector ( 15 downto 0 ) [Port] |
cal_level out std_logic_vector ( 15 downto 0 ) [Port] |
clk in std_logic [Port] |
cnt_clr in std_logic [Port] |
cnt_lat in std_logic [Port] |
cnv_mode out std_logic [Port] |
counters_pack package [Package] |
csr1_clr in std_logic [Port] |
csr2 out std_logic_vector ( 15 downto 0 ) [Port] |
csr3 out std_logic_vector ( 15 downto 0 ) [Port] |
data_adc in std_logic_vector ( 15 downto 0 ) [Port] |
dout_al out std_logic_vector ( 15 downto 0 ) [Port] |
dout_sc out std_logic_vector ( 15 downto 0 ) [Port] |
dstb in std_logic [Port] |
end_seq in std_logic [Port] |
fmdd_cmd out std_logic_vector ( 15 downto 0 ) [Port] |
fmdd_stat in std_logic_vector ( 15 downto 0 ) [Port] |
hadd in std_logic_vector ( 4 downto 0 ) [Port] |
hold_wait out std_logic_vector ( 15 downto 0 ) [Port] |
ieee library [Library] |
ierr_al in std_logic [Port] |
ierr_sc in std_logic [Port] |
l0 in std_logic [Port] |
l1_timeout out std_logic_vector ( 15 downto 0 ) [Port] |
l1_trg in std_logic [Port] |
l2_timeout out std_logic_vector ( 15 downto 0 ) [Port] |
l2_trg in std_logic [Port] |
meb_cnt in std_logic_vector ( 3 downto 0 ) [Port] |
mebs out std_logic_vector ( 4 downto 0 ) [Port] |
missed_sclk out std_logic [Port] |
paps_error in std_logic [Port] |
par_error in std_logic [Port] |
registers_block_pack package [Package] |
rstb in std_logic [Port] |
sample_div out std_logic_vector ( 15 downto 0 ) [Port] |
sclk in std_logic [Port] |
shape_bias out std_logic_vector ( 15 downto 0 ) [Port] |
shift_div out std_logic_vector ( 15 downto 0 ) [Port] |
st_cnv in std_logic [Port] |
std_logic_1164 package [Package] |
strips out std_logic_vector ( 15 downto 0 ) [Port] |
tsm_word out std_logic_vector ( 8 downto 0 ) [Port] |
us_ratio out std_logic_vector ( 15 downto 0 ) [Port] |
vfp out std_logic_vector ( 15 downto 0 ) [Port] |
vfs out std_logic_vector ( 15 downto 0 ) [Port] |
wadd in std_logic_vector ( 6 downto 0 ) [Port] |
wdata in std_logic_vector ( 15 downto 0 ) [Port] |
we in std_logic [Port] |
we_adc in std_logic [Port] |
The documentation for this class was generated from the following file:
- bc/bc_core/registers/registers.vhd
