rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Signals
missed_sclk_i	std_logic
csr2_i	std_logic_vector ( 15 downto 0 )
csr3_i	std_logic_vector ( 15 downto 0 )
dstbcnt_i	std_logic_vector ( 7 downto 0 )
sclkcnt_i	std_logic_vector ( 15 downto 0 )
l2cnt_i	std_logic_vector ( 15 downto 0 )
l1cnt_i	std_logic_vector ( 15 downto 0 )
l0cnt_i	std_logic_vector ( 15 downto 0 )
Component Instantiations
reg_block	registers_block <Entity registers_block>
cnts	counters <Entity counters>

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Member Data Documentation

cnts counters [Component Instantiation]

csr2_i std_logic_vector ( 15 downto 0 ) [Signal]

csr3_i std_logic_vector ( 15 downto 0 ) [Signal]

dstbcnt_i std_logic_vector ( 7 downto 0 ) [Signal]

l0cnt_i std_logic_vector ( 15 downto 0 ) [Signal]

l1cnt_i std_logic_vector ( 15 downto 0 ) [Signal]

l2cnt_i std_logic_vector ( 15 downto 0 ) [Signal]

missed_sclk_i std_logic [Signal]

reg_block registers_block [Component Instantiation]

sclkcnt_i std_logic_vector ( 15 downto 0 ) [Signal]

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The documentation for this class was generated from the following file:

• bc/bc_core/registers/registers.vhd