registers_block Entity Reference
Inheritance diagram for registers_block:
Collaboration diagram for registers_block:
Architectures | |
| rtl | Architecture |
| rtl2 | Architecture |
| rtl3 | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
| register_config | Package <register_config> |
| int_mstable_pack | Package <int_mstable_pack> |
Ports | |
| clk | in std_logic |
| Clock. | |
| rstb | in std_logic |
| Async reset. | |
| add_adc | in std_logic_vector ( 4 downto 0 ) |
| ADC address. | |
| we_adc | in std_logic |
| Write enable from monitor ADC. | |
| data_adc | in std_logic_vector ( 15 downto 0 ) |
| Monitor ADC data. | |
| add | in std_logic_vector ( 6 downto 0 ) |
| Register address. | |
| we | in std_logic |
| Write enable. | |
| din | in std_logic_vector ( 15 downto 0 ) |
| Register data. | |
| add_al | in std_logic_vector ( 6 downto 0 ) |
| Data out. | |
| add_sc | in std_logic_vector ( 6 downto 0 ) |
| Data out. | |
| dout_al | out std_logic_vector ( 15 downto 0 ) |
| Data out. | |
| dout_sc | out std_logic_vector ( 15 downto 0 ) |
| Data out. | |
| hadd | in std_logic_vector ( 4 downto 0 ) |
| Card address. | |
| dstbcnt_in | in std_logic_vector ( 7 downto 0 ) |
| Data strobe counts. | |
| l0cnt_in | in std_logic_vector ( 15 downto 0 ) |
| L0 counters. | |
| l1cnt_in | in std_logic_vector ( 15 downto 0 ) |
| L1 counts. | |
| l2cnt_in | in std_logic_vector ( 15 downto 0 ) |
| L2 counts. | |
| sclkcnt_in | in std_logic_vector ( 15 downto 0 ) |
| Slow clock counts. | |
| par_error | in std_logic |
| Parity error. | |
| paps_error | in std_logic |
| PASA power sup. error. | |
| alps_error | in std_logic |
| ALTRO power sup. error. | |
| al_error | in std_logic |
| ALTRO error. | |
| missed_sclk | in std_logic |
| Missed slow clock alarm. | |
| ierr_sc | in std_logic |
| I2C instruction error. | |
| ierr_al | in std_logic |
| Bus instruction error. | |
| cnt_lat | in std_logic |
| Command: Latch counters. | |
| cnt_clr | in std_logic |
| Command: Clear counters. | |
| csr1_clr | in std_logic |
| Command: Clear CSR1. | |
| bc_rst | in std_logic |
| Command: Reset BC. | |
| end_seq | in std_logic |
| End of Monitor flag. | |
| st_cnv | in std_logic |
| Command: Start monitor. | |
| fmdd_stat | in std_logic_vector ( 15 downto 0 ) |
| FMDD status. | |
| cnv_mode | out std_logic |
| Continuous conversion flag. | |
| csr2 | out std_logic_vector ( 15 downto 0 ) |
| Config/Status 2. | |
| csr3 | out std_logic_vector ( 15 downto 0 ) |
| Config/Status 3. | |
| tsm_word | out std_logic_vector ( 8 downto 0 ) |
| TSM: word. | |
| us_ratio | out std_logic_vector ( 15 downto 0 ) |
| TSM: Under sampling. | |
| bc_int | out std_logic |
| BC interrupt. | |
| bc_error | out std_logic |
| BC error. | |
| hold_wait | out std_logic_vector ( 15 downto 0 ) |
| FMD: Wait to hold. | |
| l1_timeout | out std_logic_vector ( 15 downto 0 ) |
| FMD: L1 timeout. | |
| l2_timeout | out std_logic_vector ( 15 downto 0 ) |
| FMD: L2 timeout. | |
| shift_div | out std_logic_vector ( 15 downto 0 ) |
| FMD: Shift clk. | |
| strips | out std_logic_vector ( 15 downto 0 ) |
| FMD: Strips. | |
| cal_level | out std_logic_vector ( 15 downto 0 ) |
| FMD: Cal pulse. | |
| shape_bias | out std_logic_vector ( 15 downto 0 ) |
| FMD: Shape bias. | |
| vfs | out std_logic_vector ( 15 downto 0 ) |
| FMD: Shape ref. | |
| vfp | out std_logic_vector ( 15 downto 0 ) |
| FMD: Preamp ref. | |
| sample_div | out std_logic_vector ( 15 downto 0 ) |
| FMD: Sample clk. | |
| fmdd_cmd | out std_logic_vector ( 15 downto 0 ) |
| FMD: Commands. | |
| cal_iter | out std_logic_vector ( 15 downto 0 ) |
| FMD: cal events. | |
| mebs | out std_logic_vector ( 4 downto 0 ) |
| MEB config. | |
| meb_cnt | in std_logic_vector ( 3 downto 0 ) |
| MEB counter. | |
| cal_delay | out std_logic_vector ( 15 downto 0 ) |
| FMD: xtra L1 delay. | |
Member Data Documentation
add in std_logic_vector ( 6 downto 0 ) [Port] |
Register address.
add_adc in std_logic_vector ( 4 downto 0 ) [Port] |
ADC address.
add_al in std_logic_vector ( 6 downto 0 ) [Port] |
Data out.
add_sc in std_logic_vector ( 6 downto 0 ) [Port] |
Data out.
al_error in std_logic [Port] |
ALTRO error.
alps_error in std_logic [Port] |
ALTRO power sup. error.
bc_error out std_logic [Port] |
BC error.
bc_int out std_logic [Port] |
BC interrupt.
bc_rst in std_logic [Port] |
Command: Reset BC.
cal_delay out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: xtra L1 delay.
cal_iter out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: cal events.
cal_level out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Cal pulse.
clk in std_logic [Port] |
Clock.
cnt_clr in std_logic [Port] |
Command: Clear counters.
cnt_lat in std_logic [Port] |
Command: Latch counters.
cnv_mode out std_logic [Port] |
Continuous conversion flag.
csr1_clr in std_logic [Port] |
Command: Clear CSR1.
csr2 out std_logic_vector ( 15 downto 0 ) [Port] |
Config/Status 2.
csr3 out std_logic_vector ( 15 downto 0 ) [Port] |
Config/Status 3.
data_adc in std_logic_vector ( 15 downto 0 ) [Port] |
Monitor ADC data.
din in std_logic_vector ( 15 downto 0 ) [Port] |
Register data.
dout_al out std_logic_vector ( 15 downto 0 ) [Port] |
Data out.
dout_sc out std_logic_vector ( 15 downto 0 ) [Port] |
Data out.
dstbcnt_in in std_logic_vector ( 7 downto 0 ) [Port] |
Data strobe counts.
end_seq in std_logic [Port] |
End of Monitor flag.
fmdd_cmd out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Commands.
fmdd_stat in std_logic_vector ( 15 downto 0 ) [Port] |
FMDD status.
hadd in std_logic_vector ( 4 downto 0 ) [Port] |
Card address.
hold_wait out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Wait to hold.
ieee library [Library] |
ierr_al in std_logic [Port] |
Bus instruction error.
ierr_sc in std_logic [Port] |
I2C instruction error.
int_mstable_pack package [Package] |
l0cnt_in in std_logic_vector ( 15 downto 0 ) [Port] |
L0 counters.
l1_timeout out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: L1 timeout.
l1cnt_in in std_logic_vector ( 15 downto 0 ) [Port] |
L1 counts.
l2_timeout out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: L2 timeout.
l2cnt_in in std_logic_vector ( 15 downto 0 ) [Port] |
L2 counts.
meb_cnt in std_logic_vector ( 3 downto 0 ) [Port] |
MEB counter.
mebs out std_logic_vector ( 4 downto 0 ) [Port] |
MEB config.
missed_sclk in std_logic [Port] |
Missed slow clock alarm.
numeric_std package [Package] |
paps_error in std_logic [Port] |
PASA power sup. error.
par_error in std_logic [Port] |
Parity error.
register_config package [Package] |
rstb in std_logic [Port] |
Async reset.
sample_div out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Sample clk.
sclkcnt_in in std_logic_vector ( 15 downto 0 ) [Port] |
Slow clock counts.
shape_bias out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Shape bias.
shift_div out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Shift clk.
st_cnv in std_logic [Port] |
Command: Start monitor.
std_logic_1164 package [Package] |
strips out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Strips.
tsm_word out std_logic_vector ( 8 downto 0 ) [Port] |
TSM: word.
us_ratio out std_logic_vector ( 15 downto 0 ) [Port] |
TSM: Under sampling.
vfp out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Preamp ref.
vfs out std_logic_vector ( 15 downto 0 ) [Port] |
FMD: Shape ref.
we in std_logic [Port] |
Write enable.
we_adc in std_logic [Port] |
Write enable from monitor ADC.
The documentation for this class was generated from the following file:
- bc/bc_core/registers/registers_block/registers_block.vhd
