altro_sw_mask_out Entity Reference

Inheritance diagram for altro_sw_mask_out:

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Collaboration diagram for altro_sw_mask_out:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
Ports
altro_sw	in std_logic
csr2	in std_logic_vector ( 10 downto 0 )
tsm_out	in std_logic_vector ( 7 downto 0 )
tsm_acqon	in std_logic
tsm_isol	in std_logic
rdoclk_en	out std_logic
adcclk_en	out std_logic
adc_add0	out std_logic
adc_add1	out std_logic
tsm_on	out std_logic
card_isolation	out std_logic
test_a	out std_logic
test_b	out std_logic
test_c	out std_logic
test_d	out std_logic
test_e	out std_logic
test_f	out std_logic
test_g	out std_logic
test_h	out std_logic

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Member Data Documentation

adc_add0 out std_logic [Port]

adc_add1 out std_logic [Port]

adcclk_en out std_logic [Port]

altro_sw in std_logic [Port]

card_isolation out std_logic [Port]

csr2 in std_logic_vector ( 10 downto 0 ) [Port]

ieee library [Library]

rdoclk_en out std_logic [Port]

std_logic_1164 package [Package]

test_a out std_logic [Port]

test_b out std_logic [Port]

test_c out std_logic [Port]

test_d out std_logic [Port]

test_e out std_logic [Port]

test_f out std_logic [Port]

test_g out std_logic [Port]

test_h out std_logic [Port]

tsm_acqon in std_logic [Port]

tsm_isol in std_logic [Port]

tsm_on out std_logic [Port]

tsm_out in std_logic_vector ( 7 downto 0 ) [Port]

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The documentation for this class was generated from the following file:

• bc/bc_core/altro_sw_mask_out/altro_sw_mask_out.vhd