Architectures | |
rtl | Architecture |
Libraries | |
ieee | |
Packages | |
std_logic_1164 | |
sequencer_pack | Package <sequencer_pack> |
rom_pack | Package <rom_pack> |
master_pack | Package <master_pack> |
Generics | |
MSCL_DIV | natural := 32 |
Ports | |
clk | in std_logic |
rstb | in std_logic |
stcnv | in std_logic |
we_adc | out std_logic |
end_seq | out std_logic |
wadd_adc | out std_logic_vector ( 4 downto 0 ) |
mscl | out std_logic |
msda | inout std_logic |
data_adc | out std_logic_vector ( 15 downto 0 ) |
state | out std_logic_vector ( 4 downto 0 ) |
clk in std_logic [Port] |
data_adc out std_logic_vector ( 15 downto 0 ) [Port] |
end_seq out std_logic [Port] |
ieee library [Library] |
master_pack package [Package] |
mscl out std_logic [Port] |
MSCL_DIV natural := 32 [Generic] |
msda inout std_logic [Port] |
rom_pack package [Package] |
rstb in std_logic [Port] |
sequencer_pack package [Package] |
state out std_logic_vector ( 4 downto 0 ) [Port] |
stcnv in std_logic [Port] |
std_logic_1164 package [Package] |
wadd_adc out std_logic_vector ( 4 downto 0 ) [Port] |
we_adc out std_logic [Port] |