| address_rom_i | rtl | [Signal] |
| clk | interface_adc | [Port] |
| data_adc | interface_adc | [Port] |
| data_rom_i | rtl | [Signal] |
| data_seq_i | rtl | [Signal] |
| data_valid_i | rtl | [Signal] |
| en_add_i | rtl | [Signal] |
| end_seq | interface_adc | [Port] |
| error_i | rtl | [Signal] |
| i2c_master | rtl | [Component Instantiation] |
| ieee | interface_adc | [Library] |
| instructions_rom | rtl | [Component Instantiation] |
| master_pack | interface_adc | [Package] |
| mscl | interface_adc | [Port] |
| MSCL_DIV | interface_adc | [Generic] |
| msda | interface_adc | [Port] |
| new_data_i | rtl | [Signal] |
| ready_i | rtl | [Signal] |
| rom_pack | interface_adc | [Package] |
| rstb | interface_adc | [Port] |
| rw_i | rtl | [Signal] |
| s_i | rtl | [Signal] |
| seq | rtl | [Component Instantiation] |
| sequencer_pack | interface_adc | [Package] |
| start_i | rtl | [Signal] |
| state | interface_adc | [Port] |
| stcnv | interface_adc | [Port] |
| std_logic_1164 | interface_adc | [Package] |
| stop_i | rtl | [Signal] |
| wadd_adc | interface_adc | [Port] |
| we_adc | interface_adc | [Port] |
| width_i | rtl | [Signal] |
1.6.2-20100208