interfacedec Entity Reference

Inheritance diagram for interfacedec:

[legend]

Collaboration diagram for interfacedec:

[legend]

List of all members.

Architectures
rtl	Architecture
rtl2	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
register_config	Package <register_config>
Ports
clk	in std_logic
rstb	in std_logic
add_al	in std_logic_vector ( 6 downto 0 )
data_al	in std_logic_vector ( 15 downto 0 )
wr_al	in std_logic
bcast_al	in std_logic
add_sc	in std_logic_vector ( 6 downto 0 )
data_sc	in std_logic_vector ( 15 downto 0 )
wr_sc	in std_logic
bcast_sc	in std_logic
exec	in std_logic
ackn_en_if	in std_logic
slctr	in std_logic
lastst_al	in std_logic
ierr_sc	in std_logic
cnt_lat	out std_logic
cnt_clr	out std_logic
csr1_clr	out std_logic
al_rst	out std_logic
bc_rst	out std_logic
st_cnv	out std_logic
sc_evl	out std_logic
evl_rdo	out std_logic
st_tsm	out std_logic
acq_rdo	out std_logic
ierr_al	out std_logic
add	out std_logic_vector ( 6 downto 0 )
data	out std_logic_vector ( 15 downto 0 )
we_reg	out std_logic

---

Member Data Documentation

ackn_en_if in std_logic [Port]

acq_rdo out std_logic [Port]

add out std_logic_vector ( 6 downto 0 ) [Port]

add_al in std_logic_vector ( 6 downto 0 ) [Port]

add_sc in std_logic_vector ( 6 downto 0 ) [Port]

al_rst out std_logic [Port]

bc_rst out std_logic [Port]

bcast_al in std_logic [Port]

bcast_sc in std_logic [Port]

clk in std_logic [Port]

cnt_clr out std_logic [Port]

cnt_lat out std_logic [Port]

csr1_clr out std_logic [Port]

data out std_logic_vector ( 15 downto 0 ) [Port]

data_al in std_logic_vector ( 15 downto 0 ) [Port]

data_sc in std_logic_vector ( 15 downto 0 ) [Port]

evl_rdo out std_logic [Port]

exec in std_logic [Port]

ieee library [Library]

ierr_al out std_logic [Port]

ierr_sc in std_logic [Port]

lastst_al in std_logic [Port]

numeric_std package [Package]

register_config package [Package]

rstb in std_logic [Port]

sc_evl out std_logic [Port]

slctr in std_logic [Port]

st_cnv out std_logic [Port]

st_tsm out std_logic [Port]

std_logic_1164 package [Package]

we_reg out std_logic [Port]

wr_al in std_logic [Port]

wr_sc in std_logic [Port]

---

The documentation for this class was generated from the following file:

• bc/bc_core/interfacedec/interfacedec.vhd