rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Signals
clk_master_i	std_logic
scadd_i	std_logic_vector ( 15 downto 0 )
scdata_i	std_logic_vector ( 15 downto 0 )
scexec_i	std_logic
execin_i	std_logic
exec_dcs_i	std_logic
branch_dcs_i	std_logic
bcast_dcs_i	std_logic
rnw_dcs_i	std_logic
fec_add_dcs_i	std_logic_vector ( 3 downto 0 )
bcreg_add_dcs_i	std_logic_vector ( 7 downto 0 )
bcdata_dcs_i	std_logic_vector ( 15 downto 0 )
wesmmaster_i	std_logic
weresultmaster_i	std_logic
wesm_fsc_i	std_logic
weresult_fsc_i	std_logic
seq_active_i	std_logic
nack_i	std_logic
rst_errreg_i	std_logic
errreg_i	std_logic_vector ( 1 downto 0 )
rst_resultreg_i	std_logic
weresult_i	std_logic
dataresult_i	std_logic_vector ( 20 downto 0 )
dataresult_fsc_i	std_logic_vector ( 20 downto 0 )
result_lsc_i	std_logic_vector ( 20 downto 0 )
addsm_fsc_i	std_logic_vector ( 4 downto 0 )
datasm_fsc_i	std_logic_vector ( 15 downto 0 )
addsm_i	std_logic_vector ( 4 downto 0 )
datasm_i	std_logic_vector ( 15 downto 0 )
dosm_i	std_logic_vector ( 15 downto 0 )
wesm_i	std_logic
exec_in_i	std_logic
interrupta_i	std_logic
interruptb_i	std_logic
inta_enable_i	std_logic
intb_enable_i	std_logic
inta_noten_i	std_logic
intb_noten_i	std_logic
sda_out_i	std_logic
sda_outa_i	std_logic
sda_outb_i	std_logic
sda_ack_i	std_logic
rdol_i	std_logic_vector ( 31 downto 0 ) := X " FFFFFFFF "
rdol_fsc_i	std_logic_vector ( 31 downto 0 )
we_rdol_fsc_i	std_logic
fec_al_fsc_i	std_logic_vector ( 31 downto 0 )
we_fec_al_fsc_i	std_logic
Component Instantiations
clock_master_1	msm_clock_master <Entity msm_clock_master>
sync_1	msm_sync <Entity msm_sync>
sync_2	msm_sync <Entity msm_sync>
ffd_1	msm_ffd <Entity msm_ffd>
error_module_1	msm_error_module <Entity msm_error_module>
result_1	msm_result <Entity msm_result>
ram_sm_1	msm_ram_sm <Entity msm_ram_sm>
comm_selection_1	msm_comm_selection <Entity msm_comm_selection>
lsc_core_1	msm_lsc_core <Entity msm_lsc_core>
signals_drv_1	msm_signals_drv <Entity msm_signals_drv>

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Member Data Documentation

addsm_fsc_i std_logic_vector ( 4 downto 0 ) [Signal]

addsm_i std_logic_vector ( 4 downto 0 ) [Signal]

bcast_dcs_i std_logic [Signal]

bcdata_dcs_i std_logic_vector ( 15 downto 0 ) [Signal]

bcreg_add_dcs_i std_logic_vector ( 7 downto 0 ) [Signal]

branch_dcs_i std_logic [Signal]

clk_master_i std_logic [Signal]

clock_master_1 msm_clock_master [Component Instantiation]

comm_selection_1 msm_comm_selection [Component Instantiation]

dataresult_fsc_i std_logic_vector ( 20 downto 0 ) [Signal]

dataresult_i std_logic_vector ( 20 downto 0 ) [Signal]

datasm_fsc_i std_logic_vector ( 15 downto 0 ) [Signal]

datasm_i std_logic_vector ( 15 downto 0 ) [Signal]

dosm_i std_logic_vector ( 15 downto 0 ) [Signal]

error_module_1 msm_error_module [Component Instantiation]

errreg_i std_logic_vector ( 1 downto 0 ) [Signal]

exec_dcs_i std_logic [Signal]

exec_in_i std_logic [Signal]

execin_i std_logic [Signal]

fec_add_dcs_i std_logic_vector ( 3 downto 0 ) [Signal]

fec_al_fsc_i std_logic_vector ( 31 downto 0 ) [Signal]

ffd_1 msm_ffd [Component Instantiation]

inta_enable_i std_logic [Signal]

inta_noten_i std_logic [Signal]

intb_enable_i std_logic [Signal]

intb_noten_i std_logic [Signal]

interrupta_i std_logic [Signal]

interruptb_i std_logic [Signal]

lsc_core_1 msm_lsc_core [Component Instantiation]

nack_i std_logic [Signal]

ram_sm_1 msm_ram_sm [Component Instantiation]

rdol_fsc_i std_logic_vector ( 31 downto 0 ) [Signal]

rdol_i std_logic_vector ( 31 downto 0 ) := X " FFFFFFFF " [Signal]

result_1 msm_result [Component Instantiation]

result_lsc_i std_logic_vector ( 20 downto 0 ) [Signal]

rnw_dcs_i std_logic [Signal]

rst_errreg_i std_logic [Signal]

rst_resultreg_i std_logic [Signal]

scadd_i std_logic_vector ( 15 downto 0 ) [Signal]

scdata_i std_logic_vector ( 15 downto 0 ) [Signal]

scexec_i std_logic [Signal]

sda_ack_i std_logic [Signal]

sda_out_i std_logic [Signal]

sda_outa_i std_logic [Signal]

sda_outb_i std_logic [Signal]

seq_active_i std_logic [Signal]

signals_drv_1 msm_signals_drv [Component Instantiation]

sync_1 msm_sync [Component Instantiation]

sync_2 msm_sync [Component Instantiation]

we_fec_al_fsc_i std_logic [Signal]

we_rdol_fsc_i std_logic [Signal]

weresult_fsc_i std_logic [Signal]

weresult_i std_logic [Signal]

weresultmaster_i std_logic [Signal]

wesm_fsc_i std_logic [Signal]

wesm_i std_logic [Signal]

wesmmaster_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• msmodule/msm_msmodule.vhd