msm_ram_sm Entity Reference

Inheritance diagram for msm_ram_sm:

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Collaboration diagram for msm_ram_sm:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
Ports
clk	in std_logic
address	in std_logic_vector ( 4 downto 0 )
data	in std_logic_vector ( 15 downto 0 )
we	in std_logic
q	out std_logic_vector ( 15 downto 0 )

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Member Data Documentation

address in std_logic_vector ( 4 downto 0 ) [Port]

clk in std_logic [Port]

data in std_logic_vector ( 15 downto 0 ) [Port]

ieee library [Library]

numeric_std package [Package]

q out std_logic_vector ( 15 downto 0 ) [Port]

std_logic_1164 package [Package]

we in std_logic [Port]

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The documentation for this class was generated from the following file:

• msmodule/msm_ram_sm/msm_ram_sm.vhd