rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Processes | |
| store | ( clk ) |
Constants | |
| rst_i | std_logic := ' 1 ' |
Types | |
| mem_t | array ( 25 downto 0 ) of std_logic_vector ( 15 downto 0 ) |
Signals | |
| mem_i | mem_t := ( ( others = > X " 0000 " ) ) |
Member Function Documentation
| store | ( clk ) |
Member Data Documentation
mem_t array ( 25 downto 0 ) of std_logic_vector ( 15 downto 0 ) [Type] |
rst_i std_logic := ' 1 ' [Constant] |
The documentation for this class was generated from the following file:
- msmodule/msm_ram_sm/msm_ram_sm.vhd
