msm_signals_drv Entity Reference
Inheritance diagram for msm_signals_drv:
Collaboration diagram for msm_signals_drv:
Architectures | |
| rtl | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
Ports | |
| clk | in std_logic |
| rstb | in std_logic |
| add_siu | in std_logic_vector ( 15 downto 0 ) |
| we_siu | in std_logic |
| datain_siu | in std_logic_vector ( 31 downto 0 ) |
| add_dcs | in std_logic_vector ( 15 downto 0 ) |
| we_dcs | in std_logic |
| datain_dcs | in std_logic_vector ( 31 downto 0 ) |
| dcsnsiu | in std_logic |
| addsm_fsc | in std_logic_vector ( 4 downto 0 ) |
| datasm_fsc | in std_logic_vector ( 15 downto 0 ) |
| wesm_fsc | in std_logic |
| dataresult_fsc | in std_logic_vector ( 20 downto 0 ) |
| weresult_fsc | in std_logic |
| fec_al_fsc | in std_logic_vector ( 31 downto 0 ) |
| we_fec_al_fsc | in std_logic |
| rdol_fsc | in std_logic_vector ( 31 downto 0 ) |
| we_rdol_fsc | in std_logic |
| result_lsc | in std_logic_vector ( 20 downto 0 ) |
| rdol | in std_logic_vector ( 31 downto 0 ) |
| dosm | in std_logic_vector ( 15 downto 0 ) |
| errreg | in std_logic_vector ( 1 downto 0 ) |
| inta_not_en | in std_logic |
| intb_not_en | in std_logic |
| dataout_rcuversion | in std_logic_vector ( 31 downto 0 ) |
| addsm | out std_logic_vector ( 4 downto 0 ) |
| datasm | out std_logic_vector ( 15 downto 0 ) |
| wesm | out std_logic |
| dataresult | out std_logic_vector ( 20 downto 0 ) |
| weresult | out std_logic |
| data_fec_al | out std_logic_vector ( 31 downto 0 ) |
| we_fec_al | out std_logic |
| data_rdol | out std_logic_vector ( 31 downto 0 ) |
| we_rdol | out std_logic |
| inta_enable | out std_logic |
| intb_enable | out std_logic |
| rst_errreg | out std_logic |
| rst_resultreg | out std_logic |
| rst_sclksync | out std_logic |
| dataout_msm | out std_logic_vector ( 31 downto 0 ) |
| scadd | out std_logic_vector ( 15 downto 0 ) |
| scdata | out std_logic_vector ( 15 downto 0 ) |
| scexec | out std_logic |
Member Data Documentation
add_dcs in std_logic_vector ( 15 downto 0 ) [Port] |
add_siu in std_logic_vector ( 15 downto 0 ) [Port] |
addsm out std_logic_vector ( 4 downto 0 ) [Port] |
addsm_fsc in std_logic_vector ( 4 downto 0 ) [Port] |
clk in std_logic [Port] |
data_fec_al out std_logic_vector ( 31 downto 0 ) [Port] |
data_rdol out std_logic_vector ( 31 downto 0 ) [Port] |
datain_dcs in std_logic_vector ( 31 downto 0 ) [Port] |
datain_siu in std_logic_vector ( 31 downto 0 ) [Port] |
dataout_msm out std_logic_vector ( 31 downto 0 ) [Port] |
dataout_rcuversion in std_logic_vector ( 31 downto 0 ) [Port] |
dataresult out std_logic_vector ( 20 downto 0 ) [Port] |
dataresult_fsc in std_logic_vector ( 20 downto 0 ) [Port] |
datasm out std_logic_vector ( 15 downto 0 ) [Port] |
datasm_fsc in std_logic_vector ( 15 downto 0 ) [Port] |
dcsnsiu in std_logic [Port] |
dosm in std_logic_vector ( 15 downto 0 ) [Port] |
errreg in std_logic_vector ( 1 downto 0 ) [Port] |
fec_al_fsc in std_logic_vector ( 31 downto 0 ) [Port] |
ieee library [Library] |
inta_enable out std_logic [Port] |
inta_not_en in std_logic [Port] |
intb_enable out std_logic [Port] |
intb_not_en in std_logic [Port] |
rdol in std_logic_vector ( 31 downto 0 ) [Port] |
rdol_fsc in std_logic_vector ( 31 downto 0 ) [Port] |
result_lsc in std_logic_vector ( 20 downto 0 ) [Port] |
rst_errreg out std_logic [Port] |
rst_resultreg out std_logic [Port] |
rst_sclksync out std_logic [Port] |
rstb in std_logic [Port] |
scadd out std_logic_vector ( 15 downto 0 ) [Port] |
scdata out std_logic_vector ( 15 downto 0 ) [Port] |
scexec out std_logic [Port] |
std_logic_1164 package [Package] |
we_dcs in std_logic [Port] |
we_fec_al out std_logic [Port] |
we_fec_al_fsc in std_logic [Port] |
we_rdol out std_logic [Port] |
we_rdol_fsc in std_logic [Port] |
we_siu in std_logic [Port] |
weresult out std_logic [Port] |
weresult_fsc in std_logic [Port] |
wesm out std_logic [Port] |
wesm_fsc in std_logic [Port] |
The documentation for this class was generated from the following file:
- msmodule/msm_signals_drv/msm_signals_drv.vhd
