rtl2 Architecture Reference

Inheritance diagram for rtl2:

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Collaboration diagram for rtl2:

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List of all members.

Signals
add_al_i	std_logic_vector ( 6 downto 0 )
wr_bc_i	std_logic
bc_ackn_en_i	std_logic
valid_i	std_logic
lastst_al_i	std_logic
bcast_al_i	std_logic
ierr_al_i	std_logic
wadd_i	std_logic_vector ( 6 downto 0 )
wdata_i	std_logic_vector ( 15 downto 0 )
we_reg_i	std_logic
par_error_i	std_logic
add_sc_i	std_logic_vector ( 6 downto 0 )
data_sc_i	std_logic_vector ( 15 downto 0 )
wr_sc_i	std_logic
bcast_sc_i	std_logic
ierr_sc_i	std_logic
slctr_i	std_logic
exec_i	std_logic
cnt_lat_i	std_logic
cnt_clr_i	std_logic
csr1_clr_i	std_logic
bc_rst_i	std_logic
st_cnv_i	std_logic
csr2_i	std_logic_vector ( 15 downto 0 )
start_mon_i	std_logic
end_seq_i	std_logic
add_adc_i	std_logic_vector ( 4 downto 0 )
data_adc_i	std_logic_vector ( 15 downto 0 )
we_adc_i	std_logic
cnv_mode_i	std_logic
dout_al_i	std_logic_vector ( 15 downto 0 )
dout_sc_i	std_logic_vector ( 15 downto 0 )
al_rpinc_i	std_logic
adc_state_i	std_logic_vector ( 4 downto 0 )
fmdd_stat_i	std_logic_vector ( 15 downto 0 )
slave_state_i	std_logic_vector ( 10 downto 0 )
Component Instantiations
bus_interface	altrobusinterface <Entity altrobusinterface>
	Ctrl: Enable acknowledge.
i2c_slave	slave <Entity slave>
decoder	interfacedec <Entity interfacedec>
monitors	interface_adc <Entity interface_adc>
regs	registers <Entity registers>

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Detailed Description

This architecture (implementation) of the bc_core entity does not contain code for "Test Mode" or "Scan Event Length". It's a simplification of the rtl architecture - KISS (Keep It Simple Stupid).

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Member Data Documentation

adc_state_i std_logic_vector ( 4 downto 0 ) [Signal]

add_adc_i std_logic_vector ( 4 downto 0 ) [Signal]

add_al_i std_logic_vector ( 6 downto 0 ) [Signal]

add_sc_i std_logic_vector ( 6 downto 0 ) [Signal]

al_rpinc_i std_logic [Signal]

bc_ackn_en_i std_logic [Signal]

bc_rst_i std_logic [Signal]

bcast_al_i std_logic [Signal]

bcast_sc_i std_logic [Signal]

bus_interface altrobusinterface [Component Instantiation]

Ctrl: Enable acknowledge.

Bus: Valid instruction Last state Never turn off altro_sw Pasa switch Start monitor flag. Output data Never turn off the rdo clk. Never turn on the adc clk.

cnt_clr_i std_logic [Signal]

cnt_lat_i std_logic [Signal]

cnv_mode_i std_logic [Signal]

csr1_clr_i std_logic [Signal]

csr2_i std_logic_vector ( 15 downto 0 ) [Signal]

data_adc_i std_logic_vector ( 15 downto 0 ) [Signal]

data_sc_i std_logic_vector ( 15 downto 0 ) [Signal]

decoder interfacedec [Component Instantiation]

dout_al_i std_logic_vector ( 15 downto 0 ) [Signal]

dout_sc_i std_logic_vector ( 15 downto 0 ) [Signal]

end_seq_i std_logic [Signal]

exec_i std_logic [Signal]

fmdd_stat_i std_logic_vector ( 15 downto 0 ) [Signal]

i2c_slave slave [Component Instantiation]

ierr_al_i std_logic [Signal]

ierr_sc_i std_logic [Signal]

lastst_al_i std_logic [Signal]

monitors interface_adc [Component Instantiation]

par_error_i std_logic [Signal]

regs registers [Component Instantiation]

slave_state_i std_logic_vector ( 10 downto 0 ) [Signal]

slctr_i std_logic [Signal]

st_cnv_i std_logic [Signal]

start_mon_i std_logic [Signal]

valid_i std_logic [Signal]

wadd_i std_logic_vector ( 6 downto 0 ) [Signal]

wdata_i std_logic_vector ( 15 downto 0 ) [Signal]

we_adc_i std_logic [Signal]

we_reg_i std_logic [Signal]

wr_bc_i std_logic [Signal]

wr_sc_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• bc/bc_core/bc_core.vhd