rcu Entity Reference

Inheritance diagram for rcu:

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Collaboration diagram for rcu:

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List of all members.

Architectures
busy_stim	Architecture
cnv_stim	Architecture
ctp_stim	Architecture
i2c_stim	Architecture
l0_stim	Architecture
pipe_stim	Architecture
reg_stim	Architecture
trig_stim	Architecture
Libraries
ieee
rcu_model
Packages
std_logic_1164
numeric_std
textio
rcu_misc_pack	Package <rcu_misc_pack>
Generics
HADD	std_logic_vector ( 4 downto 0 ) := " 00000 "
Ports
bd	inout std_logic_vector ( 39 downto 0 ) := ( others = > ' l ' )
writ	out std_logic
cstb	out std_logic
ackn	in std_logic
eror	in std_logic
trsf	in std_logic
dstb	in std_logic
busy	in std_logic
lvl0	out std_logic
lvl1	out std_logic
lvl2	out std_logic
grst	out std_logic
sclk	out std_logic := ' 0 '
rclk	out std_logic := ' 0 '
sda_in_a	in std_logic
sda_in_b	in std_logic
scl_a	out std_logic := ' h '
scl_b	out std_logic := ' h '
sda_out_a	out std_logic := ' h '
sda_out_b	out std_logic := ' h '

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Member Data Documentation

ackn in std_logic [Port]

bd inout std_logic_vector ( 39 downto 0 ) := ( others = > ' l ' ) [Port]

busy in std_logic [Port]

cstb out std_logic [Port]

dstb in std_logic [Port]

eror in std_logic [Port]

grst out std_logic [Port]

HADD std_logic_vector ( 4 downto 0 ) := " 00000 " [Generic]

ieee library [Library]

lvl0 out std_logic [Port]

lvl1 out std_logic [Port]

lvl2 out std_logic [Port]

numeric_std package [Package]

rclk out std_logic := ' 0 ' [Port]

rcu_misc_pack package [Package]

rcu_model library [Library]

Reimplemented from busy_stim.

scl_a out std_logic := ' h ' [Port]

scl_b out std_logic := ' h ' [Port]

sclk out std_logic := ' 0 ' [Port]

sda_in_a in std_logic [Port]

sda_in_b in std_logic [Port]

sda_out_a out std_logic := ' h ' [Port]

sda_out_b out std_logic := ' h ' [Port]

std_logic_1164 package [Package]

textio package [Package]

trsf in std_logic [Port]

writ out std_logic [Port]

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The documentation for this class was generated from the following file:

• rcu/rcu.vhd