ctp_stim Architecture Reference

Inheritance diagram for ctp_stim:

[legend]

Collaboration diagram for ctp_stim:

[legend]

List of all members.

Processes
stim	( )
counters	( rclk_i , grst_i )
read_out	( )
Libraries
rcu_model
ctp_model
Packages
rcu_pack	Package <rcu_pack>
ctp_pack
Constants
PERIOD	time := 25 ns
L1_DELAY	time := 1 us
L2_DELAY	time := 10 us
SCALE	integer := 1
RPINC_TIME	time := 2 us
Signals
rclk_i	std_logic
sclk_i	std_logic
writ_i	std_logic := ' H '
grst_i	std_logic
addr_i	std_logic_vector ( 39 downto 20 )
data_i	std_logic_vector ( 19 downto 0 )
what_i	string ( 7 downto 1 ) := ( others = > ' ' )
what_ii	string ( 7 downto 1 ) := ( others = > ' ' )
l1_delay_i	std_logic_vector ( 31 downto 0 ) := ( others = > ' 1 ' )
l2_delay_i	std_logic_vector ( 31 downto 0 ) := ( others = > ' 1 ' )
scale_i	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
busy_i	std_logic
busy_ii	std_logic := ' 1 '
lvl2_i	std_logic
rpinc_i	integer := RPINC_TIME /PERIOD
l2_cnt_i	integer := 0
do_rpinc_i	boolean := false
Component Instantiations
reset_it	reseter <Entity reseter>
rclk_clocker	clocker <Entity clocker>
sclk_clocker	clocker <Entity clocker>
trigger	ctp

---

Member Function Documentation

[Process]

counters		( rclk_i ,
		grst_i )

read_out ( ) [Process]

stim ( ) [Process]

---

Member Data Documentation

addr_i std_logic_vector ( 39 downto 20 ) [Signal]

busy_i std_logic [Signal]

busy_ii std_logic := ' 1 ' [Signal]

ctp_model library [Library]

ctp_pack package [Package]

data_i std_logic_vector ( 19 downto 0 ) [Signal]

do_rpinc_i boolean := false [Signal]

grst_i std_logic [Signal]

L1_DELAY time := 1 us [Constant]

l1_delay_i std_logic_vector ( 31 downto 0 ) := ( others = > ' 1 ' ) [Signal]

l2_cnt_i integer := 0 [Signal]

L2_DELAY time := 10 us [Constant]

l2_delay_i std_logic_vector ( 31 downto 0 ) := ( others = > ' 1 ' ) [Signal]

lvl2_i std_logic [Signal]

PERIOD time := 25 ns [Constant]

rclk_clocker clocker [Component Instantiation]

rclk_i std_logic [Signal]

rcu_model library [Library]

Reimplemented in rcu.

rcu_pack package [Package]

reset_it reseter [Component Instantiation]

rpinc_i integer := RPINC_TIME /PERIOD [Signal]

RPINC_TIME time := 2 us [Constant]

SCALE integer := 1 [Constant]

scale_i std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) [Signal]

sclk_clocker clocker [Component Instantiation]

sclk_i std_logic [Signal]

trigger ctp [Component Instantiation]

what_i string ( 7 downto 1 ) := ( others = > ' ' ) [Signal]

what_ii string ( 7 downto 1 ) := ( others = > ' ' ) [Signal]

writ_i std_logic := ' H ' [Signal]

---

The documentation for this class was generated from the following file:

• rcu/rcu_ctp.vhd