i2c_stim Architecture Reference

Inheritance diagram for i2c_stim:

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Collaboration diagram for i2c_stim:

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List of all members.

Processes
stim	( )
Procedures
	read_one( signal clk: in std_logic signal busy: in std_logic constant fec: in 15 constant reg: in 255 signal exec: out std_logic signal rnw: out std_logic signal bcast: out std_logic signal branch: out std_logic signal fec_add: out std_logic_vector ( 3 downto 0 ) signal reg_add: out std_logic_vector ( 7 downto 0 ) )
Libraries
rcu_model
msmodule2_lib
Packages
rcu_pack	Package <rcu_pack>
msm2_interface_i2c_pack	Package <msm2_interface_i2c_pack>
Constants
SCL_DELAY	time := 36 ns
SDA_IN_DELAY	time := 38 ns
SDA_OUT_DELAY	time := 28 ns
RCLK_DELAY	time := 12.5 ns
Signals
rclk_i	std_logic := ' 0 '
sclk_i	std_logic := ' 0 '
writ_i	std_logic := ' H '
grst_i	std_logic
addr_i	std_logic_vector ( 39 downto 20 )
data_i	std_logic_vector ( 19 downto 0 )
what_i	string ( 7 downto 1 ) := ( others = > ' ' )
err_reg_i	std_logic_vector ( 3 downto 0 )
A_in_i	std_logic_vector ( 15 downto 0 ) := X " dead "
B_in_i	std_logic_vector ( 15 downto 0 ) := X " beef "
result_i	std_logic_vector ( 15 downto 0 ) := ( others = > ' Z ' )
exec_i	std_logic := ' 0 '
rnw_i	std_logic := ' 0 '
bcast_i	std_logic := ' 0 '
branch_i	std_logic := ' 0 '
fec_add_i	std_logic_vector ( 3 downto 0 ) := X " 0 "
reg_add_i	std_logic_vector ( 7 downto 0 ) := X " 00 "
i2c_busy_i	std_logic
rst_i	std_logic := ' 1 '
scl_a_i	std_logic
sda_out_a_i	std_logic
sda_in_a_i	std_logic
i	integer
j	integer
Component Instantiations
msm2_interface_I2C_1	msm2_interface_I2C <Entity msm2_interface_I2C>
reset_it	reseter <Entity reseter>
rclk_clocker	clocker <Entity clocker>
sclk_clocker	clocker <Entity clocker>

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Member Function Documentation

[Procedure]

read_one		(signal clk in std_logic ,
		signal busy in std_logic ,
		constant fec in 15 ,
		constant reg in 255 ,
		signal exec out std_logic ,
		signal rnw out std_logic ,
		signal bcast out std_logic ,
		signal branch out std_logic ,
		signal fec_add out std_logic_vector(3 downto 0) ,
		signal reg_add out std_logic_vector(7 downto 0) )

stim ( ) [Process]

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Member Data Documentation

A_in_i std_logic_vector ( 15 downto 0 ) := X " dead " [Signal]

addr_i std_logic_vector ( 39 downto 20 ) [Signal]

B_in_i std_logic_vector ( 15 downto 0 ) := X " beef " [Signal]

bcast_i std_logic := ' 0 ' [Signal]

branch_i std_logic := ' 0 ' [Signal]

data_i std_logic_vector ( 19 downto 0 ) [Signal]

err_reg_i std_logic_vector ( 3 downto 0 ) [Signal]

exec_i std_logic := ' 0 ' [Signal]

fec_add_i std_logic_vector ( 3 downto 0 ) := X " 0 " [Signal]

grst_i std_logic [Signal]

i integer [Signal]

i2c_busy_i std_logic [Signal]

j integer [Signal]

msm2_interface_I2C_1 msm2_interface_I2C [Component Instantiation]

msm2_interface_i2c_pack package [Package]

msmodule2_lib library [Library]

rclk_clocker clocker [Component Instantiation]

RCLK_DELAY time := 12.5 ns [Constant]

rclk_i std_logic := ' 0 ' [Signal]

rcu_model library [Library]

Reimplemented in rcu.

rcu_pack package [Package]

reg_add_i std_logic_vector ( 7 downto 0 ) := X " 00 " [Signal]

reset_it reseter [Component Instantiation]

result_i std_logic_vector ( 15 downto 0 ) := ( others = > ' Z ' ) [Signal]

rnw_i std_logic := ' 0 ' [Signal]

rst_i std_logic := ' 1 ' [Signal]

scl_a_i std_logic [Signal]

SCL_DELAY time := 36 ns [Constant]

sclk_clocker clocker [Component Instantiation]

sclk_i std_logic := ' 0 ' [Signal]

sda_in_a_i std_logic [Signal]

SDA_IN_DELAY time := 38 ns [Constant]

sda_out_a_i std_logic [Signal]

SDA_OUT_DELAY time := 28 ns [Constant]

what_i string ( 7 downto 1 ) := ( others = > ' ' ) [Signal]

writ_i std_logic := ' H ' [Signal]

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The documentation for this class was generated from the following file:

• rcu/rcu_i2c.vhd