clock_gen Entity Reference

Inheritance diagram for clock_gen:

Collaboration diagram for clock_gen:

Architectures
rtl	Architecture
rtl2	Architecture
rtl3	Architecture
rtl4	Architecture
rtl5	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
Generics
WIDTH	integer := 8
IN_POL	std_logic := ' 1 '
CATCH	string := " y "
Ports
clk	in std_logic
rstb	in std_logic
sync	in std_logic
clk_en_o	out std_logic
clk_o	out std_logic
out_polarity	in std_logic := ' 1 '
div_phase	in std_logic_vector ( width-1 downto 0 )
div_count	in std_logic_vector ( width-1 downto 0 )

Member Data Documentation

CATCH string := " y " [Generic]

clk in std_logic [Port]

clk_en_o out std_logic [Port]

clk_o out std_logic [Port]

div_count in std_logic_vector ( width-1 downto 0 ) [Port]

div_phase in std_logic_vector ( width-1 downto 0 ) [Port]

ieee library [Library]

IN_POL std_logic := ' 1 ' [Generic]

numeric_std package [Package]

out_polarity in std_logic := ' 1 ' [Port]

rstb in std_logic [Port]

std_logic_1164 package [Package]

sync in std_logic [Port]

WIDTH integer := 8 [Generic]

The documentation for this class was generated from the following file: