rtl4 Architecture Reference

Inheritance diagram for rtl4:

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Collaboration diagram for rtl4:

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List of all members.

Processes
combinatorics	( clk_i , clk_en_i )
updater	( clk , rstb )
clocker	( clk , rstb )
Types
state_t	( idle , new_values , emit , wait_ack )
Signals
st_i	state_t
ack_new_i	boolean
old_sync_i	std_logic
cnt_i	integer range 0 to WIDTH **2-1
phase_i	integer range 0 to WIDTH **2
div_i	integer range 0 to WIDTH **2
phase_store_i	unsigned ( WIDTH-1 downto 0 )
div_store_i	unsigned ( WIDTH-1 downto 0 )
clk_i	std_logic
clk_en_i	std_logic
new_value	boolean
next_cnt_i	integer range 0 to WIDTH **2-1
next_phase_i	integer range 0 to WIDTH **2
next_div_i	integer range 0 to WIDTH **2

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Detailed Description

This architecture (implementation) defines a clock generator where the phase of the generated clock can be tuned relative to the sync input signal. sync is assumed to be a clock-like thing e.g., the sample clock of the ALTRO's.

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Member Function Documentation

[Process]

clocker		( clk ,
		rstb )

[Process]

combinatorics		( clk_i ,
		clk_en_i )

[Process]

updater		( clk ,
		rstb )

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Member Data Documentation

ack_new_i boolean [Signal]

clk_en_i std_logic [Signal]

clk_i std_logic [Signal]

cnt_i integer range 0 to WIDTH **2-1 [Signal]

div_i integer range 0 to WIDTH **2 [Signal]

div_store_i unsigned ( WIDTH-1 downto 0 ) [Signal]

new_value boolean [Signal]

next_cnt_i integer range 0 to WIDTH **2-1 [Signal]

next_div_i integer range 0 to WIDTH **2 [Signal]

next_phase_i integer range 0 to WIDTH **2 [Signal]

old_sync_i std_logic [Signal]

phase_i integer range 0 to WIDTH **2 [Signal]

phase_store_i unsigned ( WIDTH-1 downto 0 ) [Signal]

st_i state_t [Signal]

state_t ( idle , new_values , emit , wait_ack ) [Type]

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The documentation for this class was generated from the following file:

• bc/fmdd/clock_gen/clock_gen.vhd