rtl3 Architecture Reference
Inheritance diagram for rtl3:
Collaboration diagram for rtl3:
Processes | |
| combinatorics | ( clk_i , clk_en_i ) |
| clocker | ( clk , rstb ) |
Types | |
| state_t | ( setup , up , down ) |
Signals | |
| st_i | state_t |
| old_sync_i | std_logic |
| cnt_i | integer range 0 to WIDTH **2-1 |
| phase_i | integer range 0 to WIDTH **2 |
| div_i | integer range 0 to WIDTH **2 |
| phase_store_i | unsigned ( WIDTH-1 downto 0 ) |
| div_store_i | unsigned ( WIDTH-1 downto 0 ) |
| clk_i | std_logic |
| clk_en_i | std_logic |
| new_value | boolean |
Member Function Documentation
| clocker | ( clk , | |
| rstb ) |
| combinatorics | ( clk_i , | |
| clk_en_i ) |
Member Data Documentation
clk_en_i std_logic [Signal] |
clk_i std_logic [Signal] |
cnt_i integer range 0 to WIDTH **2-1 [Signal] |
div_i integer range 0 to WIDTH **2 [Signal] |
div_store_i unsigned ( WIDTH-1 downto 0 ) [Signal] |
new_value boolean [Signal] |
old_sync_i std_logic [Signal] |
phase_i integer range 0 to WIDTH **2 [Signal] |
phase_store_i unsigned ( WIDTH-1 downto 0 ) [Signal] |
state_t ( setup , up , down ) [Type] |
The documentation for this class was generated from the following file:
- bc/fmdd/clock_gen/clock_gen.vhd
