rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
combinatorics	( clk_fast_i , clk_en_i )
clk_divide	( clk , rstb , out_polarity_i , out_polarity , div_count , div_phase )
Signals
div_phase_store_i	unsigned ( WIDTH-1 downto 0 )
div_count_store_i	unsigned ( WIDTH-1 downto 0 )
div_phase_i	integer range 0 to WIDTH **2
div_count_i	integer range 0 to WIDTH **2
out_polarity_i	std_logic := ' 1 '
new_phase	boolean
clk_fast_i	std_logic
clk_en_i	std_logic
clk_cnt_i	integer range 0 to WIDTH **2-1
div_en_i	std_logic
div_fast_i	std_logic
div_cnt_i	integer range 0 to WIDTH **2-1

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Member Function Documentation

[Process]

clk_divide		( clk ,
		rstb ,
		out_polarity_i ,
		out_polarity ,
		div_count ,
		div_phase )

[Process]

combinatorics		( clk_fast_i ,
		clk_en_i )

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Member Data Documentation

clk_cnt_i integer range 0 to WIDTH **2-1 [Signal]

clk_en_i std_logic [Signal]

clk_fast_i std_logic [Signal]

div_cnt_i integer range 0 to WIDTH **2-1 [Signal]

div_count_i integer range 0 to WIDTH **2 [Signal]

div_count_store_i unsigned ( WIDTH-1 downto 0 ) [Signal]

div_en_i std_logic [Signal]

div_fast_i std_logic [Signal]

div_phase_i integer range 0 to WIDTH **2 [Signal]

div_phase_store_i unsigned ( WIDTH-1 downto 0 ) [Signal]

new_phase boolean [Signal]

out_polarity_i std_logic := ' 1 ' [Signal]

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The documentation for this class was generated from the following file:

• bc/fmdd/clock_gen/clock_gen.vhd