rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Signals
cstb_i	std_logic
write_i	std_logic
dstb_i	std_logic
trsf_i	std_logic
l1_i	std_logic
l2_i	std_logic
ackn_i	std_logic
din_i	std_logic_vector ( 39 downto 0 ) := ( others = > ' 0 ' )
sda_out_i	std_logic
paps_error_i	std_logic
alps_error_i	std_logic
al_error_i	std_logic
debug_sw_i	std_logic
bc_ackn_en_i	std_logic
bc_ackn_i	std_logic
lastst_al_i	std_logic
endtrans_i	std_logic
bc_dolo_en_i	std_logic
bc_cs_i	std_logic
al_cs_i	std_logic
wr_al_i	std_logic
dout_i	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
bc_int_i	std_logic
bc_error_i	std_logic
altro_sw_i	std_logic
pasa_sw_i	std_logic
al_rst_i	std_logic
adcclk_en_i	std_logic
tsm_on_i	std_logic
card_isolation_i	std_logic
rmtrsf_en_i	std_logic
rmtrsf_i	std_logic
rmdstb_i	std_logic
rmdata_out_i	std_logic_vector ( 39 downto 0 ) := ( others = > ' 0 ' )
mem_wren_i	std_logic
sclk_edge_i	std_logic
evl_cstb_i	std_logic
alevl_rdtrx_i	std_logic
bc_master_i	std_logic
evl_addr_i	std_logic_vector ( 39 downto 20 ) := ( others = > ' 0 ' )
or_rst_i	std_logic
al_errorb_i	std_logic
al_dolo_en_i	std_logic
al_trsf_en_i	std_logic
ackn_chrdo_i	std_logic
ric_i	std_logic
read_data_i	std_logic
fmdd_stat_i	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
l0_i	std_logic := ' 0 '
Component Instantiations
core	bc_core <Entity bc_core>
mask	altro_sw_mask_in <Entity altro_sw_mask_in>
driv	drivers <Entity drivers>

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Member Data Documentation

ackn_chrdo_i std_logic [Signal]

ackn_i std_logic [Signal]

adcclk_en_i std_logic [Signal]

al_cs_i std_logic [Signal]

al_dolo_en_i std_logic [Signal]

al_error_i std_logic [Signal]

al_errorb_i std_logic [Signal]

al_rst_i std_logic [Signal]

al_trsf_en_i std_logic [Signal]

alevl_rdtrx_i std_logic [Signal]

alps_error_i std_logic [Signal]

altro_sw_i std_logic [Signal]

bc_ackn_en_i std_logic [Signal]

bc_ackn_i std_logic [Signal]

bc_cs_i std_logic [Signal]

bc_dolo_en_i std_logic [Signal]

bc_error_i std_logic [Signal]

bc_int_i std_logic [Signal]

bc_master_i std_logic [Signal]

card_isolation_i std_logic [Signal]

core bc_core [Component Instantiation]

cstb_i std_logic [Signal]

debug_sw_i std_logic [Signal]

din_i std_logic_vector ( 39 downto 0 ) := ( others = > ' 0 ' ) [Signal]

dout_i std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) [Signal]

driv drivers [Component Instantiation]

dstb_i std_logic [Signal]

endtrans_i std_logic [Signal]

evl_addr_i std_logic_vector ( 39 downto 20 ) := ( others = > ' 0 ' ) [Signal]

evl_cstb_i std_logic [Signal]

fmdd_stat_i std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) [Signal]

l0_i std_logic := ' 0 ' [Signal]

l1_i std_logic [Signal]

l2_i std_logic [Signal]

lastst_al_i std_logic [Signal]

mask altro_sw_mask_in [Component Instantiation]

mem_wren_i std_logic [Signal]

or_rst_i std_logic [Signal]

paps_error_i std_logic [Signal]

pasa_sw_i std_logic [Signal]

read_data_i std_logic [Signal]

ric_i std_logic [Signal]

rmdata_out_i std_logic_vector ( 39 downto 0 ) := ( others = > ' 0 ' ) [Signal]

rmdstb_i std_logic [Signal]

rmtrsf_en_i std_logic [Signal]

rmtrsf_i std_logic [Signal]

sclk_edge_i std_logic [Signal]

sda_out_i std_logic [Signal]

trsf_i std_logic [Signal]

tsm_on_i std_logic [Signal]

wr_al_i std_logic [Signal]

write_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• bc/bc_only.vhd