va1_strobe Entity Reference

Inheritance diagram for va1_strobe:

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Collaboration diagram for va1_strobe:

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List of all members.

Architectures
behaviour	Architecture
Libraries
ieee
Packages
numeric_std
std_logic_1164
Ports
clk	in std_logic
rstb	in std_logic
start	in std_logic
div	in std_logic_vector ( 7 downto 0 )
phase	in std_logic_vector ( 7 downto 0 )
first	in std_logic_vector ( 7 downto 0 )
last	in std_logic_vector ( 7 downto 0 )
busy	out std_logic
shift_clk	out std_logic
shift_in	out std_logic
dreset	out std_logic

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Member Data Documentation

busy out std_logic [Port]

clk in std_logic [Port]

div in std_logic_vector ( 7 downto 0 ) [Port]

dreset out std_logic [Port]

first in std_logic_vector ( 7 downto 0 ) [Port]

ieee library [Library]

last in std_logic_vector ( 7 downto 0 ) [Port]

numeric_std package [Package]

phase in std_logic_vector ( 7 downto 0 ) [Port]

rstb in std_logic [Port]

shift_clk out std_logic [Port]

shift_in out std_logic [Port]

start in std_logic [Port]

std_logic_1164 package [Package]

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The documentation for this class was generated from the following file:

• bc/fmdd/va1_strobe/va1_strobe.vhd